Redundancy-free circuits for zero counters

An efficient method of counting the number of zeros in a plurality of 4-bit blocks which form a larger value, said method for reducing circuit redundancy comprising:

• generating three output bits q0, q1 and q2 for a given one of the 4-bit blocks from four input bits a0, a1, a2 and a3 using digital circuitry, wherein the digital circuitry carries out the logic equations
• q0=not(a1+a2+a3+a4),
• q1=not(a0+a1),
• q2=a1(not a0)+not(a0+a2),
• said generating including
• inverting the input bits to create complementary bits a0_n, a1_n, a2_n and a3_n,
• transmitting bits a0_n a1_n a2_n and a3_n to respective inputs of a first NAND gate whose output is the complement of bit q0,
• transmitting bits a0_n and a1_n to respective inputs of a second NAND gate whose output is the complement of bit q1, and
• transmitting bits a0_n and a2_n to respective inputs of a third NAND gate, and transmitting input bits a0_n and a1 respective inputs of a fourth NAND gate, wherein outputs of the third and fourth NAND gates are connected to respective inputs of a fifth NAND gate whose output is bit q2;
• combining the output bits for the given 4-bit block to yield a number of leading zeros wherein output bit q0 is the most significant bit and output bit q2 is the least significant bit;
• and
• combining the output bits from all of the 4-bit blocks to yield a count of leading zeros in the larger value wherein a most significant bit of the count is a one when all input bits from all of the 4-bit blocks are zero.