Method and apparatus for modeling multiple concurrently dispatched instruction streams in super scalar CPU with a sequential language

A computer program product in a computer readable medium for enabling the processing of a stream of instructions to be modeled using a sequential computer language, wherein the instructions are processed by means of a processor comprising a plurality of concurrently operating function units, each function unit being provided with its own unit clock, said computer program product comprising:

• first instructions for generating a model master clock having a master clock cycle;
• second instructions for initializing each of said function units at the beginning of respectively corresponding processing cycles;
• third instructions for operating each function unit during its corresponding processing cycle to carry out a task with respect to one of said instructions, in order to produce a task result, wherein said function units are operated concurrently with one another, each according to its own unit clock, and said unit clocks are unsynchronized with one another;
• fourth instructions for completing the processing cycles of all of said function units at the same specified time, as defined by a specified position of one of said master clock cycles, by selectively evaluating the task result results respectively produced by each of said function units;
• and
• fifth instructions for writing each of said evaluated results produced by said function units, together with said specified time defined by said specified master clock cycle position, into registers corresponding to said task results.

A computer system comprising:

• a processor comprising a plurality of function units, wherein each function unit is provided with its own unit clock, and said function units are operated concurrently to process a stream of instructions;
• and
• a computer readable medium connected to the processor, said medium including further processor instructions configured to be read by said processor and to thereby cause said processor to:
• generate a model master clock having a master clock cycle;
• initialize each of said function units at the beginning of respectively corresponding processing cycles;
• operate each function unit during its corresponding processing cycle to carry out a task with respect to one of said instructions of said instruction stream, in order to produce a task result, wherein said function units are operated concurrently with one another, each according to its own unit clock, and said unit clocks are unsynchronized with one another;
• complete the processing cycles all of said function units at the same specified time as defined by a specified position of one of said master clock cycles, by selectively evaluating the task results respectively produced by each of said function units;
• and
• write each of said evaluated results produced by said function units, together with said specified time defined by said specified master clock cycle position, into registers respectively corresponding to said task results, so that processing of said instruction stream can be modeled using a sequential computer language.