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AssigneeMitsubishi Electric Corporation
InventorsMinoru Saeki, Daisuke Suzuki
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It is a purpose to evaluate a tamper resistance of an actual circuit with a high accuracy and at a high speed in an upstream process of a circuit design. A tamper resistance evaluating apparatus includes a signal change time counter unit 10 for counting the number of times a signal in a logic circuit changes, a power consumption calculation unit 20 for calculating a power consumption in the logic circuit based on the number of times a signal changes, which is counted by the signal change time counter unit, a leaked-information analysis unit 80 for analyzing information leaked from the logic circuit based on the power consumption in the logic circuit calculated by the power consumption calculation unit, a file database 40 for storing a file used by a simulator 30, a simulation control information producing unit 50 for producing control information for controlling the logic simulator 30, a time sequence electric power information producing unit 60 for producing time sequence electric power information, in which the power consumptions calculated by the power consumption calculation unit 20 are arranged in a time sequence, and a result displaying unit 70 for displaying the time sequence electric power information.
An electric power calculating apparatus for calculating a power consumption comprising:
An electric power calculating method for calculating a power consumption comprising:
A tamper resistance evaluating apparatus for detecting a leakage of information from a logic circuit, and for evaluating a tamper resistance of a logic circuit, the tamper resistance evaluating apparatus comprising:
A tamper resistance evaluating method, wherein a leaked-information evaluating method for evaluating a leakage of information from a circuit is performed, the tamper resistance evaluating method comprising:
Dependencies are inferred from the claim text.