Bi-modal RF architecture for low power devices

A bi-modal RF receiver configured to reduce power consumption, comprising:

• a low noise amplifier having a first and second modes operable for biasing an analog circuit processing a wireless signal, the first mode providing lower biasing and consuming less power than the second mode;
• a phase locked loop in communication with the low noise amplifier and having a first mode of low phase noise and second mode of high phase noise, the first mode of low phase noise of the phased locked loop consuming more power than the second mode of high phase noise;
• a multi-stage baseband filter coupled to receive the wireless signal and operable in a first mode for bypassing at least one stage of the multi-stage baseband filter to reduce power consumption by the multi-stage baseband filter, the multi-stage baseband filter operable in a second non-bypass mode to consume more power;
• an analog-to-digital converter in communication with the multi-stage baseband filter, the analog-to-digital converter operable in a first mode to conserve power by adjusting the number of digital bits used when converting the wireless signal from analog and operable in a second mode to use more digital bits and consume more power;
• and
• a power control logic component to monitor the wireless signal and, based on a characteristic of the wireless signal, to reduce power consumed to process the wireless signal by promoting use of the first modes of one or more of the low noise amplifier, the phase locked loop, the multi-stage baseband filter, and analog-to-digital converter.