Differential signal strength detector

A method for signal detection comprises:

• rectifying an input signal to produce a rectified input signal;
• rectifying a reference signal to produce a rectified reference signal;
• combining the rectified input signal and the rectified reference signal to produce a combined signal;
• filtering the combined signal to produce a digital representation of the input signal;
• coupling a positive leg of the rectified input signal to a negative leg of the rectified reference signal;
• and
• coupling a negative leg of the rectified input signal to a positive leg of the rectified reference signal.

A multi-gigabit transceiver (MGT) comprises:

• a transmitter section operably coupled to convert outbound parallel data into high speed outbound serial data;
• a receiver section, when enabled, operably coupled to convert inbound high speed serial data into inbound parallel data;
• and
• a signal detection circuit operably coupled to enable the receiver section when presence of a signal is detected, wherein the signal detection circuit includes:
• a first signal multiplier operably coupled to square an input signal to produce a squared input signal, wherein at least a portion of the input signal corresponds to the inbound high speed serial data;
• a second signal multiplier operably coupled to square a reference signal to produce a squared reference signal;
• and
• a filter module operably coupled to produce an indication of signal detection based on the squared input signal and the squared reference signal,
• wherein each of the first and second signal multipliers include a transistor section operably coupled to receive the input signal or the reference signal, and a high impedance load operably coupled to the transistor section to provide an output.

A signal detection circuit comprises:

• a first rectifying module operably coupled to rectify the input signal to produce a rectified input signal;
• a second rectifying module operably coupled to rectify a reference signal to produce a rectified reference signal;
• a combining module operably coupled to combine the rectified input signal and the rectified reference signal to produce a combined signal;
• and
• a filtering module operably coupled to filter the combined signal to produce a digital value representation of the input signal,
• wherein the filter module includes a capacitor operably coupled to filter the combined signal to produce a logic one when a magnitude of the rectified input signal is a first threshold level above the rectified reference signal and to produce a logic zero when the magnitude of the rectified input signal is a second threshold level below the rectified reference signal.