Device and method for synchronous data transmission using reference signal

A data receiver for receiving parallel data of plural bits transmitted from a transmitter, the data receiver comprising:

• a synchronous signal generating circuit which generates a receiver synchronous signal using a reference signal;
• a pattern detecting circuit which detects a training pattern transmitted in synchronization with a transmitter synchronous signal generated by the transmitter using the reference signal;
• a clock adjusting circuit which generates an adjusted clock signal for each bit of the parallel data by adjusting a phase of a first clock signal using each one of one-bit data signals each consisting of a single bit of the parallel data, so that a setup time and a hold time are ensured for each one-bit data signal;
• a data buffer circuit which loads each one-bit data signal in accordance with the adjusted clock signal and holds a predetermined number of bits of the data consecutive in time, and whose memory position is initialized when the training pattern is detected;
• and
• a read circuit which selects data of plural bits stored in the data buffer circuit in time sequence and reads out the selected data as parallel data, in accordance with a second clock signal and in synchronization with the receiver synchronous signal.

A system comprising a plurality of data transmitter-receivers which transmit/receive parallel data of plural bits to/from one another, each of the data transmitter-receivers comprising:

• a synchronous signal generating circuit which generates a synchronous signal using a reference signal distributed to the plurality of data transmitter-receivers;
• a pattern generating circuit which generates a training pattern for each bit of the parallel data, in synchronization with the synchronous signal;
• an output circuit which transmits the training pattern and the parallel data bit by bit to other data transmitter-receiver as a receiving end;
• a pattern detecting circuit which detects the training pattern transmitted in synchronization with a synchronous signal generated using the reference signal in one of the data transmitter-receivers as a transmitting end;
• a clock adjusting circuit which generates an adjusted clock signal for each bit of the parallel data transmitted from the data transmitter-receiver as the transmitting end, by adjusting a phase of a first clock signal using each one of one-bit data signals each consisting of a single bit of the parallel data, so that a setup time and a hold time are ensured for the each one-bit data signal;
• a data buffer circuit which loads each one-bit data signal in accordance with the adjusted clock signal, and holds a predetermined number of data bits consecutive in time, and whose memory position is initialized when the training pattern is detected;
• and
• a read circuit which selects data of plural bits stored in the data buffer circuit in time sequence and reads out the selected data as parallel data, in accordance with a second clock signal and in synchronization with the synchronous signal generated by the synchronous signal generating circuit.

A system comprising a plurality of data transmitter-receivers which transmit/receive parallel data of plural bits to/from one another, each of the data transmitter-receiver comprising:

• a synchronous signal generating circuit which generates a synchronous signal using a reference signal distributed to the plurality of data transmitter-receivers;
• a pattern generating circuit which generates a training pattern for each bit of the parallel data, in synchronization with the synchronous signal;
• an output circuit which transmits the training pattern and the parallel data bit by bit to other data transmitter-receiver as a receiving end;
• a pattern detecting circuit which detects the training pattern transmitted in synchronization with a synchronous signal generated using the reference signal in one of the data transmitter-receivers as a transmitting end;
• a clock adjusting circuit which generates an adjusted clock signal for each bit of the parallel data transmitted from the data transmitter-receiver as the transmitting end, by adjusting a phase of a first clock signal using each one of one-bit data signals each consisting of a single bit of the parallel data, so that a setup time and a hold time are ensured for the each one-bit data signal;
• a data buffer circuit which loads each one-bit data signal in accordance with the adjusted clock signal, and holds a predetermined number of data bits consecutive in time;
• and
• a read circuit which selects data of plural bits stored in the data buffer circuit in time sequence and reads out the selected data as parallel data, in accordance with a second clock signal, and
• wherein the plurality of transmitter-receivers perform a synchronous transmission of the parallel data, using the synchronous signal generated by the synchronous signal generating circuit, and the training pattern.

A data transmission method for transmitting parallel data of plural bits from a transmitter to a receiver, comprising:

• on the part of the transmitter, generating a transmitter synchronous signal using a reference signal;
• generating a training pattern for each bit of the parallel data, in synchronization with the synchronous signal;
• and
• transmitting the training pattern and the parallel data bit by bit to the receiver, and
• on the part of the receiver, generating a receiver synchronous signal using the reference signal;
• initializing a memory position of a data buffer circuit when the training pattern is detected;
• generating an adjusted clock signal for each bit of the parallel data by adjusting a phase of a first clock signal using each one of one-bit data signals each consisting of a single bit of the parallel data, so that a setup time and a hold time are ensured for the each one-bit data signal;
• loading each one-bit data signal into the data buffer circuit in accordance with the adjusted clock signal, to hold a predetermined number of data bits consecutive in time in the data buffer circuit;
• and
• selecting data of plural bits stored in the data buffer circuit in time sequence and reading out the selected data as parallel data, in accordance with a second clock signal.

A data transmitter for transmitting parallel data of plural bits to a receiver, the data transmitter comprising:

• a synchronous signal generating circuit which generates a transmitter synchronous signal using a reference signal;
• a pattern generating circuit which generates a training pattern for each bit of the parallel data, in synchronization with the synchronous signal;
• and
• an output circuit which transmits the training pattern and the parallel data bit by bit to the receiver, in which a receiver synchronous signal is generated using the reference signal, a memory position of a data buffer circuit is initialized when the training pattern is detected, an adjusted clock signal is generated for each bit of the parallel data by adjusting a phase of a first clock signal using each one of one-bit data signals each consisting of a single bit of the parallel data, so that a setup time and a hold time are ensured for each one-bit data signal, each one-bit data signal is loaded into the data buffer circuit in accordance with the adjusted clock signal, to hold a predetermined number of data bits consecutive in time in the data buffer circuit, and data of plural bits stored in the data buffer circuit is selected in time sequence and read out as parallel data in accordance with a second clock signal.

A data receiver for receiving parallel data of plural bits transmitted from a transmitter, the data receiver comprising:

• a synchronous signal generating circuit which generates a receiver synchronous signal using a reference signal;
• a pattern detecting circuit which detects a training pattern transmitted in synchronization with a transmitter synchronous signal generated using the reference signal in the transmitter;
• a clock adjusting circuit which generates an adjusted clock signal for each bit of the parallel data by adjusting a phase of a first clock signal using each one of one-bit data signals each consisting of a single bit of the parallel data, so that a setup time and a hold time are ensured for the each one-bit data signal;
• a data buffer circuit which loads each one-bit data signal in accordance with the adjusted clock signal, and holds a predetermined number of data bits consecutive in time, and whose memory position is initialized when the training pattern is detected;
• and
• a read circuit which selects data of plural bits stored in the data buffer circuit in time sequence and reads out the selected data as parallel data, in accordance with a second clock signal and in synchronization with the receiver synchronous signal.