Memory devices having reduced coupling noise between wordlines
AssigneeMicron Technology, Inc.
InventorsTae H. Kim, Charles L. Ingalls, Howard C. Kirsch, Jeremy J. Gum
Life of this patent
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Abstract
Memory devices configured to reduce coupling noise between adjacent wordlines in a memory array. More specifically, wordline drivers are interleaved such that adjacent wordlines are driven by wordline drivers enabled by different row decoders. Each wordline driver includes a weak transistor to ground and a strong transistor to ground. By disabling the wordline driver on the wordlines directly adjacent to the active wordlines, a path is provided to drive the coupling noise from the active wordline to ground through the strong transistor.
Claims20
A memory device comprising:
- a first plurality of wordline drivers, wherein each of the first plurality of wordline drivers is configured to receive an enable signal from a first row decoder and configured to drive a respective wordline;
- and
- a second plurality of wordline drivers, wherein each of the second plurality of wordline drivers is configured to receive an enable signal from a second row decoder and configured to drive a respective wordline, and
- wherein the first plurality of wordline drivers is interleaved with the second plurality of wordline drivers, and wherein each of the first plurality of wordline drivers is directly adjacent to at least one of the second plurality of wordline drivers.
A memory device comprising:
- a first wordline driver coupled to a first wordline and configured to receive a first enable signal from a first row decoder;
- a second wordline driver coupled to a second wordline and configured to receive a second enable signal from a second row decoder, wherein the second wordline is immediately adjacent to the first wordline, and wherein the second wordline driver is immediately adjacent to the first wordline driver;
- and
- a third wordline driver coupled to a third wordline and configured to receive the first enable signal from the first row decoder, wherein the third wordline is immediately adjacent to the second wordline.
A memory device comprising:
- a memory array comprising a plurality of wordlines;
- a first wordline driver arranged on a first side of the memory array and configured to drive a first of the plurality of wordlines;
- a second wordline driver arranged on the first side of the memory array directly adjacent to the first wordline driver and configured to drive a second of the plurality of wordlines, wherein the second of the plurality of wordlines is directly adjacent to the first of the plurality of wordlines;
- a first row decoder configured to transmit a first enable signal to the first wordline driver;
- and
- a second row decoder configured to transmit a second enable signal to the second wordline driver.
Dependencies are inferred from the claim text.