Circuit and method for reducing power in a memory device during standby modes
AssigneeMicron Technology, Inc.
InventorAaron M. Schoenfeld
Life of this patent
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Abstract
A memory device responsive to standby mode commands for reducing internal operational power on a memory device is disclosed. The memory device includes a circuit for reducing power during a standby mode with the circuit including a reference with at least first and second reference signals. The circuit also includes a switching device for switching between the first and second reference signals in response to the standby mode command and further controls an internal operational power regulator to adjust between normal and low-power outputs further reducing the power to portions of the memory device.
Claims14
A circuit, comprising:
- a fully operational mode reference signal and a standby mode reference signal;
- and
- a DC-to-DC voltage regulator responsive to a switchably connected one of the fully operational mode reference signal and the standby mode reference signal for generating operational power to a dynamic memory device, the switchably connected one determined at least in part on a refresh state of the dynamic memory device.
A method for reducing power in a memory device, comprising:
- switchably regulating an operational power in response to one of a hilly operational mode reference signal and a standby mode reference signal;
- and
- powering circuitry exclusive to self-refresh circuitry on the memory device with the operational power.
A circuit for reducing power in a dynamic memory device, comprising:
- circuitry exclusive to self-refresh circuitry on the dynamic memory device;
- and
- a DC-to-DC regulator alternatively down-regulating operational power to at least a portion of the circuitry exclusive to the self-refresh circuitry in response to a standby mode.
Dependencies are inferred from the claim text.