Semiconductor memory device
AssigneeMatsushita Electric Industrial Co., Ltd.
InventorHiroyuki Sadakata
Life of this patent
Estimating the term…
Abstract
Through setting an internal test mode, a refresh operation for a DRAM is carried out by externally inputted address signals, instead of internally generated address signals, while maintaining the same number of memory cell arrays to be activated as that of memory cell arrays which are concurrently activated in a refresh for memory cell arrays. This configuration needs no drastic addition of circuits and allows a reduction in disturb test time for a plurality of memory cell arrays.
Claims6
A semiconductor memory device comprising a plurality of memory cell arrays, each of which includes a memory cell group and a sense amplifier circuit, the device comprising:
- selecting means for concurrently selecting two or more memory cell arrays from among the plurality of memory cell arrays in response to a command, which is externally inputted, for selecting an automatic data refresh operation for the memory cell group;
- refreshing means for, in each of the selected two or more memory cell arrays, refreshing data in the memory cell group connected to word lines corresponding to address signals which are internally generated in an automatic manner;
- and
- switching means for, during the automatic data refresh operation, switching address signals for selecting word lines from address signals internally generated in an automatic manner to address signals externally inputted.
A semiconductor memory device comprising a plurality of memory cell arrays, each of which includes a memory cell group and a sense amplifier circuit, the device comprising:
- selecting means for concurrently selecting two or more memory cell arrays from among the plurality of memory cell arrays in response to a command, which is externally inputted, for selecting an automatic data refresh operation for the memory cell group;
- refreshing means for, in each of the selected two or more memory cell arrays, refreshing data in the memory cell group connected to word lines corresponding to address signals which are internally generated in an automatic manner;
- and
- disconnecting means for, during a read operation, concurrently selecting memory cell arrays, a number of which is equal to a number of memory cell arrays which are activated in the automatic data refresh operation and for disconnecting the sense amplifier circuit and data lines.
A semiconductor memory device comprising a plurality of memory cell arrays, each of which includes a memory cell group and a sense amplifier circuit, the device comprising:
- first selecting means for concurrently selecting two or more memory cell arrays from among the plurality of memory cell arrays in response to a command, which is externally inputted, for selecting an automatic data refresh operation for the memory cell group;
- first refreshing means for, in each of the selected two or more memory cell arrays, refreshing data in the memory cell group connected to word lines corresponding to address signals which are internally generated in an automatic manner;
- second refreshing means for selecting the memory cell arrays connected to word lines corresponding to address signals externally inputted and for refreshing the selected memory cell arrays;
- and
- second selecting means for, during the refresh operation by the externally inputted address signals, selecting memory cell arrays, a number of which is equal to a number of the memory cell arrays which are activated in the automatic data refresh operation.
Dependencies are inferred from the claim text.