Semiconductor integrated circuit device
AssigneeKabushiki Kaisha Toshiba
InventorKoji Kohara
Life of this patent
Estimating the term…
Abstract
There is disclosed a semiconductor integrated circuit comprising a plurality of memory macros each including a redundancy cell, each of the memory macros being assigned with an address and transferred with data of a defect address of a semiconductor memory and store the data of the defect address, a plurality of non-volatile memory elements less in number than the plurality of memory macros, each of which stores redundancy data to be transferred to a memory macro and address data showing the memory macro as a transfer destination of the redundancy data in a form of set, and a transfer control circuit which transfers the redundancy data to the memory macro as the transfer destination from the non-volatile memory elements in accordance with the address data showing the memory macro as the transfer destination.
Claims20
A semiconductor integrated circuit comprising:
- a plurality of memory macros each including a redundancy cell, each of the memory macros being assigned with an address and transferred with data of a defect address of a semiconductor memory and store the data of the defect address;
- a plurality of non-volatile memory elements less in number than the plurality of memory macros, each of which stores redundancy data to be transferred to a memory macro and address data showing the memory macro as a transfer destination of the redundancy data in a form of set;
- and
- a transfer control circuit which transfers the redundancy data to the memory macro as the transfer destination from the non-volatile memory elements in accordance with the address data showing the memory macro as the transfer destination.
A semiconductor integrated circuit comprising:
- a plurality of first latch circuits which are serially transferred with data of defect address of a semiconductor memory and store the data of the defect address;
- a memory macro which includes a plurality of second latch circuits serially connected to the first latch circuits and assigned with address and having the same configuration as the first latch circuits and equal in number to the first latch circuits, the data of the defect address of the semiconductor memory being transferred to the second latch circuits and stored in the second latch circuits;
- a plurality of non-volatile memory elements less than in number the second latch circuits, and stores redundancy data to be transferred to the second latch circuits and address data showing the transfer destination of the redundancy data in a form of set;
- a control circuit initializing the second latch circuits using data “0”;
- and
- a transfer control circuit which transfers in parallel, to a second latch circuit whose address data is stored in the non-volatile memory elements, redundancy data in a form of set with the address data in accordance with the address data, and thereafter serially transfers the data stored in the second latch circuits to the first latch circuits.
A semiconductor integrated circuit comprising:
- a plurality of patterns of a plurality of first latch circuits which are serially transferred with data of defect address of a semiconductor memory and store the data of the defect address;
- a pattern of a memory macro which includes a plurality of second latch circuits serially connected to the first latch circuits and assigned with address and having the same configuration as the first latch circuits and equal in number to the first latch circuits, the data of the defect address of the semiconductor memory being transferred to the second latch circuits and stored in the second latch circuits;
- a plurality of patterns of a plurality of non-volatile memory elements less than in number the second latch circuits, and stores redundancy data to be transferred to the second latch circuits and address data showing the transfer destination of the redundancy data in a form of set;
- a pattern of a control circuit initializing the second latch circuits using data “0”;
- and
- a pattern of a transfer control circuit which transfers in parallel, to a second latch circuit whose address data is stored in the non-volatile memory elements, redundancy data in a form of set with the address data in accordance with the address data, and thereafter serially transfers the data stored in the second latch circuits to the first latch circuits.
Dependencies are inferred from the claim text.