Semiconductor storage device
AssigneeInternational Business Machines Corporation
InventorToshio Sunaga
Life of this patent
Estimating the term…
Abstract
The objective of the present invention is to provide a DRAM that reduces the current consumed by an address comparison circuit that compares an address signal with a defective address signal that has been programmed. Redundant predecoders predecode a defective row address signal DRA output by program circuits, and an address comparison circuit compares a predecoded signal, output by a predecoder, with the defective predecoded signals PDRA, output by the redundant predecoders. In the case of a 2-bit predecoding system, the address comparison circuit compares the predecoded signal PRA with the defective predecoded signal PDRA using four bits in order to compare the row address signal RA with the defective row address signal DRA using groups of two bits.
Claims7
A semiconductor storage device comprising:
- a plurality of selection lines (WL);
- a spare selection line (SWL);
- a program circuit (24) which programs a defective address and generates a defective address signal (DRA) indicating a defective address has been programmed;
- an address comparison circuit (26) which compares a plurality of bits comprising an address signal (RA) with a plurality of corresponding bits of the defective address signal (DRA);
- if the bits of the address signal (RA) and the defective address signal (DRA) match, activating a first match signal (DIS), or if the bits of the address signal and the defective address signal do not match, deactivating the first match signal (DIS);
- a decoder (14) which is activated in accordance with the deactivation of the first match signal (DIS) and drives the plurality of selection lines (WL) in accordance with the address signal (RA);
- and
- a spare decoder (20), for driving the spare selection line (SWL) in accordance with the activation of the first match signal (DIS).
A semiconductor storage device comprising:
- a plurality of memory cells arranged along rows and along columns;
- a plurality of selection lines (WL) and spare word lines (SWL) arranged in rows;
- a plurality of column selection lines (CSL) arranged along columns;
- a column decoder (16) for driving the column selection lines (CSL) in accordance with a column address signal;
- a program circuit (24), for programming a defective row address, and for generating a defective row address signal (DRA) indicating a defective row address has been programmed, the defective row address signal comprising a plurality of defective row address bits;
- an address comparison circuit (54), for comparing a row address signal comprising a plurality of row address bits with a plurality of corresponding defective row address bits, and, if the pluralities and row address and defective row address bits match, activating a first match signal (DIS), or if the pluralities and row address and defective row address bits do not match, deactivating the first match signal (DIS);
- a row decoder (14), which is activated in accordance with the deactivation of the first match signal (DIS) to drive the selection lines in accordance with the row address signal;
- and
- a spare row decoder (20), for driving the spare selection line (SWL) when the first match signal is activated (DIS).
Dependencies are inferred from the claim text.