Semiconductor device, semiconductor memory device and data strobe method

A method of controlling a data strobe (DQS) in a semiconductor device having an interface of an open drain type or a pseudo-open drain type, the method comprising:

• generating a first DQS control signal that is activated for a second predetermined time while the clock signal is activated during a following section next to a postamble section of a data strobe signal;
• generating a second DQS control signal;
• changing a state of the following section next to the postamble section of the data strobe signal in response to a clock signal, the first DQS control signal and the second DQS control signal, sequentially from a first logical state of the postamble section to a second logical state;
• and
• changing the state of the following section next to the postamble section of the data strobe signal sequentially from the second logical state to a high impedance state after a first predetermined time wherein the second logical state is different than the high impedance state.

A semiconductor device having an interface of an open drain type or a pseudo-open drain type, the semiconductor device comprising:

• a data strobe (DQS) control signal generating circuit configured to generate a first DQS control signal and a second DQS control signal;
• a DQS control circuit configured to control a data strobe signal DQS by sequentially changing a state of a following section next to a postamble section of the data strobe signal DQS in response to a clock signal, the first DQS control signal and the second DQS control signal, from a first logical state of the postamble section to a second logical state, and from the second logical state to a high impedance state after a first predetermined time wherein the second logical state is different than the high impedance state;
• and
• an output unit configured to output the data strobe signal DQS,
• wherein the first DQS control signal is activated for a second predetermined time while the clock signal is activated during the following section next to the postamble section,
• wherein the DQS control signal generating circuit configured to generate the second DQS control signal by latching a third DQS control signal in response to the clock signal and an inverted clock signal having an inverted phase with respect to the clock signal, and then by delaying the third DQS control signal for a first delay time, and
• wherein the first DQS control signal is generated by executing an OR operation of the third DQS control signal and a fourth DQS control signal, the fourth DQS control signal being generated by latching the second DQS control signal and by delaying the third DQS control signal for a second delay time.

A semiconductor device having an interface of an open drain type or a pseudo-open drain type, the semiconductor device comprising:

• a data strobe (DQS) control signal generating circuit configured to generate a first DQS control signal and a second DQS control signal;
• a DQS control circuit configured to control a data strobe signal DQS by sequentially changing a state of a following section next to a postamble section of the data strobe signal DQS in response to a clock signal, the first DQS control signal and the second DQS control signal, from a first logical state of the postamble section to a second logical state, and from the second logical state to a high impedance state after a first predetermined time wherein the second logical state is different than the high impedance state;
• and
• an output unit configured to output the data strobe signal DQS,
• wherein the first DQS control signal is activated for a second predetermined time while the clock signal is activated during the following section next to the postamble section,
• wherein the DQS control signal generating circuit configured to generate the second DQS control signal by latching a third DQS control signal in response to the clock signal and an inverted clock signal having an inverted phase with respect to the clock signal, and then by delaying the third DQS control signal for a first delay time,
• wherein the first predetermined time corresponds to a half period of the clock signal, and
• wherein the DQS control signal generating circuit comprises:
• a first latch configured to latch the third DQS control signal;
• a second latch configured to latch an output of the first latch;
• a third latch configured to latch an output of the second latch;
• and
• a first delay circuit configured to delay an output of the third latch for the first delay time to output the second DQS control signal.

A semiconductor device having an interface of an open drain type or a pseudo-open drain type, the semiconductor device comprising:

• a data strobe (DQS) control signal generating circuit configured to generate a first DQS control signal and a second DQS control signal;
• a DQS control circuit configured to control a data strobe signal DQS by sequentially changing a state of a following section next to a postamble section of the data strobe signal DQS in response to a clock signal, the first DQS control signal and the second DQS control signal, from a first logical state of the postamble section to a second logical state, and from the second logical state to a high impedance state after a first predetermined time wherein the second logical state is different than the high impedance state;
• and
• an output unit configured to output the data strobe signal DQS,
• wherein the first DQS control signal is activated for a second predetermined time while the clock signal is activated during the following section next to the postamble section,
• wherein the DQS control circuit comprises:
• a first DQS control circuit configured to maintain the second logic state of the postamble section of the data strobe signal while both the first DQS control signal is activated and the clock signal is activated;
• and
• a second DQS control circuit configured to maintain the first logic state of the postamble section of the data strobe signal while the second DQS control signal is activated and the clock signal is not activated,
• wherein the first DQS control circuit comprises a NAND gate configured to execute a NAND operation of the first DQS control signal and the clock signal, and
• wherein the second DQS control signal comprises an AND gate configured to execute an AND operation of the first DQS control circuit and an inverted clock signal having an inverted phase with respect to the clock signal.

A method of controlling a data strobe (DQS) in a semiconductor device having an interface of an open drain type or a pseudo-open drain type, the method comprising:

• generating a first DQS control signal that is activated for a second predetermined time while the clock signal is activated during a following section next to a postamble section of a data strobe signal;
• generating a second DQS control signal;
• changing a state of the following section next to the postamble section of the data strobe signal in response to a clock signal, the first DQS control signal and the second DQS control signal, from a first logical state of the postamble section to a second logical state;
• and
• changing the state of the following section next to the postamble section of the data strobe signal from the second logical state to a high impedance state after a first predetermined time wherein the second logical state is different than the high impedance state,
• wherein generating a second DQS control signal corresponds to generating the second DQS control signal by latching a third DQS control signal in response to the clock signal and an inverted clock signal having an inverted phase with respect to the clock signal, and then by delaying the third DQS control signal for a first delay time,
• wherein the first DQS control signal is generated by executing an OR operation of the third DQS control signal and a fourth DQS control signal, the fourth DQS control signal being generated by latching the second DQS control signal and by delaying the third DQS control signal for a second delay time.