Flash memory device and erasing method thereof

A method of post-programming a flash memory device, comprising the steps of:

• (a) selecting a word line from a plurality of word lines in response to an address;
• (b) post-programming memory cells of the selected word line in a predetermined post-programming unit;
• (c) determining, after incrementing the address, whether the incremented address matches one of a plurality of reference addresses;
• (d) varying the post-programming unit of the selected memory cells whenever the incremented address matches one of the plurality of reference addresses;
• and
• (e) repeating the steps (a) through (d) until all word lines are selected.

A flash memory device having a memory cell array with memory cells arranged in rows and columns, comprising:

• a row decoder selecting the rows in response to a row address;
• a column decoder selecting the columns in response to a column address;
• write drivers divided into a plurality of groups for driving the selected columns with a bit line voltage;
• a column address generator counting a number of post-programming operations and generating the column address and a count-up pulse signal;
• a row address generator configured to store a plurality of reference addresses, generating the row address in response to the count-up pulse signal;
• and
• a selection circuit generating selection signals to activate each of the write driver groups in response to a counted value of the count-up pulse signal,
• wherein the row address generator outputs flag information indicating a change of column selection unit whenever the row address matches one of the plurality of reference addresses, and
• wherein the selection circuit controls activation of the selection signals in accordance with the flag information so as to increase a number of the memory cells to be post-programmed in the selected columns.