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US 7,460,411 B2Granted
Array source line (AVSS) controlled high voltage regulation for programming flash or EE array
AssigneeAtmel Corporation
InventorEmil Lambrache
Life of this patent
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Abstract
A method for programming a Flash memory array comprises coupling at least one of a current source and a potential source to at least one selected bitline of a Flash memory array, monitoring a potential VAVSS of an array VSS line by means of a comparator, allowing the array VSS line to electrically float until the potential VAVSS is approximately equal to a reference potential Vref, and terminating the programming by de-coupling at least one of the current source and the potential source.
Claims5
A method for erasing a Flash memory array, the method comprising:
- in a Flash memory cell comprising a select transistor and a double gate transistor, the select transistor including a drain terminal coupled to a bitline, a gate terminal coupled to a word line, and a source terminal coupled to a drain terminal of the double gate transistor, the double gate transistor further including a control gate terminal coupled to a select line and a source terminal coupled to an array VSS line, the array VSS line being configured to electrically float during a portion of a programming operation until a potential VAVSS of the array VSS line approximately matches a reference voltage Vref, applying a potential of approximately zero volts to the select line;
- applying a word line potential VWL to the word line in order to bias the select transistor into conduction;
- applying a bitline potential VBL of approximately zero volts to the bitline;
- fixing the array VSS potential VAVSS at approximately zero volts;
- increasing a select line potential VSL applied to the select line from approximately zero volts to an erasing potential in a controlled time interval;
- maintaining the select line potential VSL at the erasing potential for an erase time interval;
- and
- returning the select line potential VSL to approximately zero volts in a controlled time interval.
5 more elements
A method for erasing a flash memory array, the method comprising:
- in a flash memory array having an array VSS line coupled to a comparator, the comparator monitoring a potential VAVSS of the array during a programming operation, coupling a potential of approximately zero volts to a source terminal and a drain terminal of a double gate transistor, the double gate transistor further including a control gate and a floating gate;
- coupling a potential VSL to the control gate of the double gate transistor;
- varying the potential VSL from an initial value of approximately zero volts to an elevated potential, the elevated potential chosen in conjunction with a first coupling ratio and a second coupling ratio of the double gate transistor such that a potential VFG of the floating gate reaches an approximately constant value independent of an initial state of the floating gate;
- and
- returning the potential VSL to approximately zero volts to produce an erased value for the potential VFG.
2 more elements
Dependencies are inferred from the claim text.