Semiconductor memory device of single-bit-line drive type
AssigneeKabushiki Kaisha Toshiba
InventorTomoaki Yabe
Life of this patent
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Abstract
A semiconductor memory device includes a plurality of word lines, first and second bit lines, a plurality of memory cells which are connected to the first and second bit lines, a differential amplifier which is connected to one end of the first bit line and one end of the second bit line, a reference-current generating circuit which is connected to the other end of the second bit line and which generates a reference-current smaller than the cell current of the memory cells, and a dummy word line which is connected to the reference-current generating circuit, to activate the reference-current generating circuit in order to read data.
Claims14
A semiconductor memory device comprising:
- a plurality of word lines;
- first and second bit lines;
- a plurality of memory cells which are connected to the first and second bit lines, each memory cell having:
- a first inverter having an input terminal and an output terminal;
- a second inverter having an input terminal connected to the output terminal of the first inverter, and an output terminal connected to the input terminal of the first inverter;
- a first transfer-gate transistor having a gate terminal connected to one of the word lines, and a first current path connected at one end to the first bit line and at the other end to at least the output terminal of the first inverter;
- a second transfer-gate transistor having a gate terminal connected to one of the word lines, and a second current path connected at one end to the second bit line and at the other end to at least the output terminal of the second inverter;
- a third transfer-gate transistor having a gate terminal connected to one of the word lines, and a third current path connected at one end to the first bit line;
- and
- a reading-driver transistor having a gate terminal connected to at least the input terminal of the first inverter, and a fourth current path connected at one end to the other end of the third current path of the third transfer-gate transistor, and at the other end to a first power-supply terminal;
- a differential amplifier which is connected to one end of the first bit line and one end of the second bit line;
- a reference-current generating circuit which is connected to the other end of the second bit line and which generates a reference-current smaller than the cell current of the memory cells;
- and
- a dummy word line which is connected to the reference-current generating circuit, to activate the reference-current generating circuit in order to read data.
Dependencies are inferred from the claim text.