Semiconductor memory device which generates voltages corresponding to a plurality of threshold voltages
AssigneeKabushiki Kaisha Toshiba
InventorNoboru Shibata
Life of this patent
Estimating the term…
Abstract
A memory cell MC stores a plurality of bits of data using threshold levels 1, 2, . . . , n (n is a natural number). A storage section stores a plurality of items of parameter data for generating the threshold levels. An arithmetic circuit generates voltage data for generating voltages corresponding to the threshold levels by accumulating the parameter data read from the storage section. A voltage generating circuit generates a voltage on the basis of the voltage data generated by the arithmetic circuit. The arithmetic circuit, when reading data from the memory cell at threshold level k (k<=n), generates the voltage data by accumulating parameter data at the threshold levels i to k (i<=k).
Claims20
A semiconductor memory device comprising:
- a memory cell which stores a plurality of bits of data using threshold levels 1, 2, . . . , n (n is a natural number);
- a storage section which stores a plurality of items of parameter data for generating the threshold levels;
- an arithmetic circuit which calculates voltage data for generating voltages corresponding to the threshold levels by accumulating the parameter data read from the storage section;
- and
- a voltage generating circuit which generates a voltage on the basis of the voltage data calculated by the arithmetic circuit,
- wherein the arithmetic circuit, when reading data from the memory cell at threshold level k (k<=n), generates the voltage data by accumulating parameter data at the threshold levels i to k (i<=k).
A semiconductor memory device comprising:
- a memory cell array in which a plurality of memory cells connected to word lines and bit lines are arranged in a matrix;
- and
- a control circuit which controls the potentials on the word lines and the bit lines and which, in a read operation of reading data from the memory cells, activates unselected word lines adjacent to selected one of the word lines and then activates a selected word line.
A semiconductor memory device comprising:
- a memory cell array which includes NAND cells having a plurality of memory cells and a plurality of select gates connected in series;
- a voltage generating circuit which supplies a potential to the word lines of the NAND cells on the basis of a reference voltage;
- and
- a varying circuit which varies the potential of the reference voltage,
- wherein the varying circuit outputs a first reference voltage when a specific memory cell of the NAND cells is written into and outputs a second reference voltage different from the first reference voltage when a memory cell different from the specific memory cell is written into.
A semiconductor memory device comprising:
- a memory cell which stores data using threshold levels;
- an arithmetic circuit which adds first and second parameter data or subtracts one from the other, the first parameter data being data for generating a first level for first reading or verify reading and the second parameter data being data on the difference between a second level different from the first level and for second reading or verify reading and the first level;
- and
- a voltage generating circuit which generates a voltage on the basis of the voltage data calculated by the arithmetic circuit,
- wherein the voltage generating circuit generates a voltage on the basis of the first parameter data when reading data from the memory cell at the first level or performing verify reading, the arithmetic circuit adds parameter data of the first level and second parameter data about the difference between the first level and the second level, or subtracts one from the other, and the voltage generating circuit generates a voltage on the basis of the data obtained from the addition or subtraction.
Dependencies are inferred from the claim text.