Method for checking block erasing of a memory and circuit thereof

A method for erasing a block of memory cells of a memory including a memory array in which memory cells are arranged according to word lines and according to bit columns transverse to the word lines, and a sense amplifier for supplying a unique signal representative of a conductive or non-conductive state of one of the memory cells, the memory cells of a bit column being coupled to a common bit line, each memory cell having a floating-gate transistor and an access transistor coupled to the floating-gate transistor, the method comprising:

• selecting memory cells, each having the floating-gate transistor and the access transistor coupled to the floating-gate transistor, to be erased by selecting a word line and several bit lines coupled to said memory cells to be erased;
• erasing the selected memory cells by putting them into the non-conductive state;
• and
• checking a state of the erased memory cells by:
• coupling the sense amplifier simultaneously to all of the selected bit lines;
• and
• supplying by the sense amplifier a global state of all of the memory cells coupled to said selected bit lines to which the sense amplifier is coupled, if the memory cells coupled to said selected bit lines are all simultaneously in said non-conductive state.

A memory, comprising:

• memory cells arranged in a memory array according to word lines and according to bit columns transverse to the word lines, the memory cells of a bit column being coupled to a common bit line, each memory cell having a floating-gate transistor and an access transistor coupled to the floating-gate transistor;
• selection means for selecting at least one word line and at least one bit line;
• a sense amplifier to supply a unique signal representative of a conductive or non-conductive state of a memory cell belonging to a selected bit line to which the sense amplifier is coupled;
• and
• switch means for coupling the selected bit line to the sense amplifier, wherein the selection and switch means are respectively adapted to select simultaneously several bit lines and to couple the sense amplifier simultaneously to the selected bit lines, the sense amplifier being adapted to supply a global state of all of the memory cells belonging to the selected bit lines to which the sense amplifier is coupled, if the memory cells coupled to said selected bit lines are all simultaneously in said non-conductive state.

A method for checking a state of a group of memory cells arranged in a memory array arranged according to word lines and according to bit columns transverse to the word lines, the method comprising:

• grouping together a plurality of memory cells into a set, each memory cell having a floating-gate transistor and an access transistor coupled to the floating-gate transistor;
• selecting the set by selecting at least one word line and several bit lines in the set;
• coupling a sense amplifier simultaneously to the selected bit lines in the set;
• supplying by the sense amplifier a global state of the memory cells in the set that are coupled to the selected bit lines to which the sense amplifier is coupled, if each memory cell in the set is simultaneously non-conductive;
• and
• checking the global state.

A memory, comprising:

• memory cells arranged in a memory array according to word lines and according to bit columns transverse to the word lines, each memory cell having a floating-gate transistor and an access transistor coupled to the floating-gate transistor;
• means for grouping together a plurality of memory cells into a set;
• means for selecting the set by selecting at least one word line and several bit lines in the set;
• sense amplifier means for supplying a unique signal representative of a conductive or non-conductive state of a memory cell belonging to a selected bit line in the set to which the sense amplifier means is coupled;
• and
• means for selectively coupling the sense amplifier means to the selected bit line in the set so as to supply a global state of the memory cells belonging to the selected bit line in the set, if each memory cell belonging to the selected bit line in the set is simultaneously in said non-conductive state.