Programming a memory with varying bits per cell
AssigneeMicron Technology, Inc.
InventorsFrankie F. Roohparvar, Vishal Sarin, Jung S. Hoei
Life of this patent
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Abstract
Memory devices adapted to receive and transmit analog data signals representative of two or more bits, such as to facilitate increases in data transfer rates relative to devices communicating data signals indicative of individual bits. A controller and a read/write channel convert the digital bit patterns to analog data signals to be stored in a memory array at a particular bit capacity level in order to achieve a desired level of reliability.
Claims20
A method for programming a solid state memory device having a memory array coupled to a controller, the method comprising:
- determining a bit capacity level that provides a reliability level for data to be stored in the memory array;
- transmitting to the controller a digital data signal of the data to be stored;
- converting the digital data signal into an analog data signal that is indicative of the digital data signal;
- and
- writing the analog data signal to the memory array at the bit capacity level.
A method for programming a solid state memory device having a memory array coupled to a controller having a digital-to-analog conversion circuit, the method comprising:
- generating a plurality of reliability levels, each with a corresponding bit capacity level, for a plurality of representative cells of the memory array;
- determining a desired reliability level for a received digital bit pattern in response to a type of the data;
- determining an area of the memory array comprising the representative cell having the reliability level of the plurality of reliability levels that is at least substantially equal to the desired reliability level;
- converting the digital bit pattern to an analog data signal that is indicative of the bit pattern;
- and
- writing the analog data signal to the area of the memory array using the corresponding bit capacity level.
A solid state memory device, comprising:
- an array of non-volatile memory cells having columns of memory cells coupled to bit lines and rows of memory cells coupled to word lines;
- a read/write channel having digital-to-analog conversion circuitry and analog-to-digital conversion circuitry;
- and
- control circuitry for the array of non-volatile memory cells wherein the control circuitry is adapted to program the memory cells by determining a reliability level for data to be written to the array of memory cells, determining a bit capacity level that provides the reliability level, converting a digital bit pattern to be stored into an analog data signal, through the read/write channel, and writing the analog data signal to the memory array at the bit capacity level.
Dependencies are inferred from the claim text.