Back to results
US 7,460,395 B1Granted
Thyristor-based semiconductor memory and memory array with data refresh
AssigneeT-RAM Semiconductor, Inc.
InventorsHyun-Jin Cho, Farid Nemati
Life of this patent
Estimating the term…
Abstract
A new memory cell can contain only a single thyristor. There is no need to include an access transistor in the cell. In one embodiment, the thyristor is a thin capacitively coupled thyristor. The new memory cell can be connected to word, bit, and control lines in several ways to form different memory arrays. Timing and voltage levels of word, bit and control lines are disclosed.
Claims10
A memory array comprising:
- at least one word line;
- at least one bit line;
- at least one third line;
- at least one thyristor having an anode, a cathode, and at least one base region, the anode being connected to one of the at least one word line, bit line and third line, the cathode being connected to another of the at least one word line, bit line, and third line, and the at least one base region being capacitively coupled to remaining of the at least one word line, bit line and third line;
- a word line controller selectably operable to apply a word line bias to the at least one word line;
- a sense amp and bit line controller selectable operable to sense/apply a bit line bias of/to the at least one bit line;
- a write enable controller selectably operable to apply a write-enable bias to the at least one third line;
- and
- a read/write controller operable to periodically select and drive the word line controller, the sense amp and bit line controller and the write enable controller to refresh the at least one thyristor and restore the respective state of its then first or second operative states.
6 more elements
Dependencies are inferred from the claim text.