Semiconductor memory device and semiconductor integrated circuit
AssigneeRenesas Technology Corp.
InventorsYasuhiko Takahashi, Takayuki Tanaka
Life of this patent
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Abstract
In a semiconductor memory device, third and fourth transistors are configured as a vertical structure. The third transistor is laminated over a first transistor, and the fourth transistor is laminated over a second transistor, whereby a reduction in cell area is achieved. A voltage, which is set on the condition that the difference between a source potential applied to each of the first and second transistors and the potential of a select level of a word line becomes greater than or equal to a threshold voltage of each of the third and fourth transistors, is supplied to a source electrode of each of the first and second transistors, to thereby perform “0” write compensation.
Claims6
A semiconductor memory device comprising:
- a first memory cell area in which first memory cells are disposed in an array form;
- a second memory cell area in which second memory cells different in structure from the first memory cells are disposed in an array form;
- and
- a peripheral circuit shared between the first memory cell area and the second memory cell area,
- wherein said each first memory cell includes:
- a storage section comprising an n channel type first MOS transistor and an n channel type second MOS transistor connected to each other;
- a p channel type third MOS transistor that is capable of connecting a drain electrode of the first MOS transistor and a gate electrode of the second MOS transistor to a first bit line;
- and
- a p channel type fourth MOS transistor that is capable of connecting a drain electrode of the second MOS transistor and a gate electrode of the first MOS transistor to the first bit line,
- wherein the third and fourth MOS transistors are configured as a vertical structure, the third MOS transistor is laminated over the first MOS transistor, and the fourth MOS transistor is laminated over the second MOS transistor,
- wherein said each second memory cell includes a storage section in which a first inverter comprising a p channel type fifth MOS transistor and an n channel type sixth MOS transistor, both connected in series, and a second inverter comprising a p channel type seventh MOS transistor and an n channel type eighth MOS transistor, both connected in series, are connected in a loop form, and
- wherein the fifth and seventh MOS transistors are configured as a vertical structure, the fifth MOS transistor is laminated over the sixth MOS transistor, and the seventh MOS transistor is laminated over the eighth MOS transistor.
Dependencies are inferred from the claim text.