High-speed serial interface architecture for a programmable logic device
AssigneeAltera Corporation
InventorsThungoc M. Tran, Yu Xu, Kwong-Wen Wei, Sergey Shumarayev
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Abstract
A high-speed serial interface for a programmable logic device includes a plurality of features to handle the various issues that may arise with data rates over 1 Gbps and particularly over 1.25 Gbps. Those features may include dynamic phase alignment to control clock-data skew, data realignment (e.g., bit slip circuitry) to account for channel-to-channel skew, full-duplex serializer and deserializer, out-of-range frequency support for low frequencies, and a soft-CDR mode.
Claims32
A serial data interface for use with a programmable logic device, said serial data interface being adapted to receive and deserialize a serial data signal, said serial data interface comprising:
- a clock source that provides a clocking signal having a plurality of phases;
- a dynamic phase alignment module that operates on serial data input to said interface and on said plurality of phases of said clocking signal to align said serial data with one of said phases of said clock signal to which it is closest in phase and to provide a phase-aligned data signal and to output said one of said phases as a phase-aligned clock signal;
- a clock tree module that derives a data clock using said clocking signal;
- serial data processing circuitry to deserialize said data signal based on an input clock signal;
- and
- a clock selector that selects one of said data clock and said phase-aligned clock signal as said input clock signal.
A programmable logic device comprising:
- a programmable logic core;
- a clock source that provides a clocking signal having a plurality of phases;
- at least one serial data interface being adapted to receive and deserialize a serial data signal, and to output said deserialized data signal to said programmable logic core, each said serial data interface comprising:
- a dynamic phase alignment module that operates on serial data input to said interface and on said plurality of phases of said clocking signal to align said serial data with one of said phases of said clocking signal to which it is closest in phase and to provide a phase-aligned data signal and to output said one of said phases as a phase-aligned clock signal,
- a clock tree module that derives a data clock using said clocking signal,
- serial data processing circuitry to deserialize said data signal based on an input clock signal, and
- a clock selector that selects one of said data clock and said phase-aligned clock signal as said input clock signal.
A serial data interface for use with a programmable logic device, said serial data interface being adapted to receive and deserialize a serial data signal, said serial data interface comprising:
- a clock source that provides a clocking signal having a plurality of phases;
- a dynamic phase alignment module that operates on serial data input to said interface and on said plurality of phases of said clocking signal to align said serial data with one of said phases of said clock signal to which it is closest in phase and to provide a phase-aligned data signal and to output said one of said phases as a phase-aligned clock signal;
- a clock tree module that derives a data clock using said clocking signal;
- and
- serial data processing circuitry to deserialize said data signal based on an input clock signal;
- wherein:
- said dynamic phase alignment module operates at a lower clock rate than said serial data processing circuitry;
- each said serial data interface further comprising:
- clock dividing circuitry on an output of said clock source that divides each phase of said clocking signal by a division factor for use by said dynamic phase alignment module.
A programmable logic device comprising:
- a programmable logic core;
- a clock source that provides a clocking signal having a plurality of phases;
- at least one serial data interface being adapted to receive and deserialize a serial data signal, and to output said deserialized data signal to said programmable logic core, each said serial data interface comprising:
- a dynamic phase alignment module that operates on serial data input to said interface and on said plurality of phases of said clocking signal to align said serial data with one of said phases of said clock signal to which it is closest in phase and to provide a phase-aligned data signal and to output said one of said phases as a phase-aligned clock signal;
- a clock tree module that derives a data clock using said clocking signal;
- and
- serial data processing circuitry to deserialize said data signal based on an input clock signal;
- wherein:
- said dynamic phase alignment module operates at a lower clock rate than said serial data processing circuitry;
- each said serial data interface further comprising:
- clock dividing circuitry on an output of said clock source that divides each phase of said clocking signal by a division factor for use by said dynamic phase alignment module.
Dependencies are inferred from the claim text.