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US 7,459,982 B2Granted
EMI reduction stage in a post-amplifier
AssigneeFinisar Corporation
InventorJason Y Miao
Life of this patent
Estimating the term…
Abstract
An amplifier output stage for reducing Electromagnetic Interference (EMI) that includes an output node and an input node. A first transistor has a base terminal coupled to the input node and has a collector terminal coupled to the output node. A second transistor has a base terminal coupled to an emitter terminal of the first transistor and has a collector terminal coupled to the output node. A third transistor has a collector terminal coupled to the emitter terminal of the first transistor and the base of the second transistor and has an emitter terminal coupled to a current source and to an emitter terminal of the second transistor. A resistor has a first terminal coupled to a base terminal of the third transistor and has a second terminal coupled to the emitter terminal of the first transistor.
Claims24
An amplifier output stage for reducing Electromagnetic Interference (EMI) comprising:
- an output node;
- an input node configured to receive a data signal;
- a first transistor having a base terminal coupled to the input node and having a collector terminal coupled to the output node;
- a second transistor having a base terminal coupled to an emitter terminal of the first transistor and having a collector terminal coupled to the output node;
- a third transistor having a collector terminal coupled to the emitter terminal of the first transistor and the base of the second transistor and having an emitter terminal coupled to a current source and to an emitter terminal of the second transistor;
- and
- a resistor having a first terminal coupled to a base terminal of the third transistor and a having a second terminal coupled to the emitter terminal of the first transistor, the base terminal of the second transistor and the collector terminal of the third transistor.
4 more elements
An amplifier output stage for reducing Electromagnetic Interference (EMI) comprising:
- a first output node;
- a first input node configured to receive a first data signal;
- a second output node;
- a second input node configured to receive a second data signal that is complementary to the first data signal;
- a first transistor having a base terminal coupled to the first input node and having a collector terminal coupled to the first output node;
- a second transistor having a base terminal coupled to an emitter terminal of the first transistor and having a collector terminal coupled to the first output node;
- a third transistor having a collector terminal coupled to the emitter terminal of the first transistor and the base of the second transistor and having an emitter terminal coupled to a first current source and to an emitter terminal of the second transistor;
- a first resistor having a first terminal coupled to a base terminal of the third transistor and a having a second terminal coupled to the emitter terminal of the first transistor, the base terminal of the second transistor and the collector terminal of the third transistor;
- a fourth transistor having a base terminal coupled to the second input node and having a collector terminal coupled to the second output node;
- a fifth transistor having a base terminal coupled to an emitter terminal of the fourth transistor and having a collector terminal coupled to the second output node;
- a sixth transistor having a collector terminal coupled to the emitter terminal of the fourth transistor and the base of the fifth transistor and having an emitter terminal coupled to a second current source and to an emitter terminal of the fifth transistor;
- and
- a second resistor having a first terminal coupled to a base terminal of the sixth transistor and having a second terminal coupled to the emitter terminal of the fourth transistor, the base terminal of the fifth transistor and the collector terminal of the sixth transistor.
10 more elements
An amplifier output stage for reducing Electromagnetic Interference (EMI) comprising:
- an output node;
- an input node configured to receive a data signal;
- a first transistor having a base terminal coupled to the input node and having a collector terminal coupled to the output node;
- a second transistor having a base terminal coupled to an emitter terminal of the first transistor and having a collector terminal coupled to the output node;
- a third transistor having a collector terminal coupled to the emitter terminal of the first transistor and the base of the second transistor and having an emitter terminal coupled to a current source and to an emitter terminal of the second transistor;
- a first resistor having a first terminal coupled to a base terminal of the third transistor and a having a second terminal coupled to the emitter terminal of the first transistor, the base terminal of the second transistor and the collector terminal of the third transistor;
- and
- an output filter coupled to the output node.
5 more elements
An amplifier output stage for reducing Electromagnetic Interference (EMI) comprising:
- a first output node;
- a first input node configured to receive a first data signal;
- a second output node;
- a second input node configured to receive a second data signal that is complementary to the first data signal;
- a first transistor having a gate terminal coupled to the first input node and having a drain terminal coupled to the first output node;
- a second transistor having a gate terminal coupled to an source terminal of the first transistor and having a drain terminal coupled to the first output node;
- a third transistor having a drain terminal coupled to the source terminal of the first transistor and the gate of the second transistor and having an source terminal coupled to a first current source and to an source terminal of the second transistor;
- a first resistor having a first terminal coupled to a gate terminal of the third transistor and a having a second terminal coupled to the source terminal of the first transistor, the gate terminal of the second transistor and the drain terminal of the third transistor;
- a fourth transistor having a gate terminal coupled to the second input node and having a drain terminal coupled to the second output node;
- a fifth transistor having a gate terminal coupled to an source terminal of the fourth transistor and having a drain terminal coupled to the second output node;
- a sixth transistor having a drain terminal coupled to the source terminal of the fourth transistor and the gate of the fifth transistor and having an source terminal coupled to a second current source and to an source terminal of the fifth transistor;
- and
- a second resistor having a first terminal coupled to a gate terminal of the sixth transistor and having a second terminal coupled to the source terminal of the fourth transistor, the gate terminal of the fifth transistor and the drain terminal of the sixth transistor.
10 more elements
Dependencies are inferred from the claim text.