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US 7,459,951 B2Granted
Self-calibrating digital pulse-width modulator (DPWM)
AssigneeExar Corporation
InventorAleksandar Prodic
Life of this patent
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Abstract
A hybrid digital pulse width modulator can have a delay line with digitally programmable delay cells. The digitally programmable delay cells can be adjusted by a digital correction signal from a delay matching circuit.
Claims16
A hybrid digital pulse width modulator comprising:
- clocked logic to indicate a first portion of a switching period;
- unclocked logic to indicate a second portion of a switching period, the unclocked logic including a delay line, the delay line including digitally programmable delay cells adjustable with a digital correction signal;
- a delay matching circuit using a delay line replica to produce the digital correction signal, wherein an output signal is produced with a duty cycle determined from the first and second portion;
- and
- wherein the digital correction signal is a multi-bit value which turns on or off different sized transistors in the delay cells.
2 more elements
A hybrid digital pulse width modulator comprising:
- clocked logic to indicate a first portion of a switching period;
- unclocked logic to indicate a second portion of a switching period, the unclocked logic including a delay line, the delay line including digitally programmable delay cells adjustable with a digital correction signal;
- a delay matching circuit using a delay line replica to produce the digital correction signal, wherein an output signal is produced with a duty cycle determined from the first and second portion;
- wherein the delay line replica is used to set the speed of the delay cells;
- and
- wherein the delay line replica is one half plus one the size of the delay line and is triggered by both edges of a clock.
3 more elements
A hybrid digital pulse width modulator comprising:
- clocked logic to indicate a first portion of a switching period;
- unclocked logic to indicate a second portion of a switching period, the unclocked logic including a delay line, the delay line including digitally programmable delay cells adjustable with a digital correction signal;
- a delay matching circuit using a delay line replica to produce the digital correction signal, wherein an output signal is produced with a duty cycle determined from the first and second portion;
- and
- wherein the delay line replica is one delay cell longer than the delay line and the delay line replica is triggered by the same edge of two successive clock periods.
2 more elements
A digital pulse width modulator receiving a duty ratio value comprising:
- duty logic to produce an output after a period of time corresponding to most significant bits of the duty ratio value;
- a delay line receiving the output of the duty logic including digitally programmable delay cells, the delay line used to produce an output after a second period of time corresponding to least significant bits of the delay ratio value;
- a delay matching circuit including a delay line replica used to adjust the transistors turned on in the delay cells to adjust the delay;
- wherein the delay line replica produces a digital correction signal for the delay line;
- and
- wherein the delay matching circuit produces a multi bit value which turns on or off different sized transistors in the delay cell.
3 more elements
A digital pulse width modulator receiving a duty ratio value comprising:
- duty logic to produce an output after a period of time corresponding to most significant bits of the duty ratio value;
- a delay line receiving the output of the duty logic including digitally programmable delay cells, the delay line used to produce an output after a second period of time corresponding to least significant bits of the delay ratio value;
- a delay matching circuit including a delay line replica used to adjust the transistors turned on in the delay cells to adjust the delay;
- wherein the delay line replica produces a digital correction signal for the delay line;
- wherein the delay line replica is used to set the speed of the delay line;
- and
- wherein the delay line replica is one half plus one the size of the delay line and is triggered by both edges of a clock.
4 more elements
A digital pulse width modulator receiving a duty ratio value comprising:
- duty logic to produce an output after a period of time corresponding to most significant bits of the duty ratio value;
- a delay line receiving the output of the duty logic including digitally programmable delay cells, the delay line used to produce an output after a second period of time corresponding to least significant bits of the delay ratio value;
- a delay matching circuit including a delay line replica used to adjust the transistors turned on in the delay cells to adjust the delay;
- wherein the delay line replica produces a digital correction signal for the delay line;
- and
- wherein the delay line replica is one delay cell longer than the delay line and the delay line replica is triggered by the same edge of two successive clock periods.
3 more elements
A digital pulse width modulator receiving a duty ratio value comprising:
- duty logic to produce an output after a period of time corresponding to most significant bits of the duty ratio value;
- a delay line receiving the output of the duty logic including digitally programmable delay cells, the delay line used to produce an output after a second period of time corresponding to least significant bits of the delay ratio value;
- a delay matching circuit including a delay line replica used to adjust the transistors turned on in the delay cells to adjust the delay;
- wherein the delay line replica produces a digital correction signal for the delay line, further comprising set-reset logic associated with the duty logic and the delay line to produce the output of the DPWM.
1 more element
Dependencies are inferred from the claim text.