Phase adjustment for a divider circuit
AssigneeSilicon Laboratories Inc.
InventorSrisai Rao Seethamraju
Life of this patent
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Abstract
A divider circuit receives an input signal and at least one phase adjustment control signal and supplies a phase adjustable output signal. The divider circuit includes a state machine providing N states, with no phase adjustment, to provide as the output signal the input signal divided by N. Each state of the state machine lasts for one period of the input signal. The divider circuit adjusts the phase of the output signal by changing the number of states that occur in one period of the output signal. In response to a control signal to decrement the phase of the output signal, the state machine skips at least one state for one period of the output signal. In response to a control signal to increment the phase of the output signal, the state machine inserts one or more states for one period of the output signal.
Claims14
A method for adjusting a phase of an output signal of a divider circuit including a state machine, the method comprising:
- receiving an input signal at an input of the divider circuit that receives one or more phase adjust control signals;
- when the one or more phase adjust control signals indicate no phase adjust, dividing the input signal by N utilizing N states of the state machine in the divider circuit to provide the output signal equal to the input signal divided by N, N being an integer greater than 2;
- in response to one of the one or more phase adjust signals indicating a phase adjust, implementing a phase adjust of the output signal by adjusting a number of states that occur in the state machine of the divider circuit;
- in response to the phase adjust being a phase decrement indication, implementing a phase decrement by bypassing at least one of the N states to generate one period of the output signal having N−1 or fewer input signal periods for the one period of the output signal;
- and
- in response to the phase adjust being a phase increment indication, implementing a phase increment by introducing at least one additional state to the N states for one period of the output signal to cause the output signal to have N+1 or more input signal periods for the one period of the output signal.
A divider circuit coupled to receive an input signal and at least one phase adjustment control signal and supply an output signal, the divider circuit comprising:
- a state machine providing N states, with no phase adjustment, to provide as the output signal the input signal divided by N, each state lasting for one period of the input signal;
- and
- wherein the divider circuit is responsive to a phase adjustment control signal to adjust a number of states that occur in one period of the output signal to adjust a phase of the output signal.
An apparatus comprising:
- means for dividing, when phase adjust signals are unasserted, an input signal by N utilizing N state transitions, N being an integer greater than 2 and supplying an output signal representing the input signal divided by N;
- and
- wherein the means for dividing includes means for implementing a phase adjust in response to one of the phase adjust signals being asserted, by adjusting a number of state transitions that occur in the means for dividing, and wherein in response to a phase adjust signal indicating a decrement of a phase of the output signal at least one state transition of the means for dividing is skipped and in response to a phase adjust signal indicating an increment of the phase of the output signal, at least one extra state transition is inserted in the state transitions occurring during a period of the output signal.
Dependencies are inferred from the claim text.