High accuracy sample and hold circuit having a common negative input terminal

A high accuracy sample and hold circuit, suitable for sampling an input signal and outputting an output signal;

• the circuit comprising:
• a first switch, comprising a first terminal for receiving the input signal, for connecting the input signal to a second terminal thereof during a first period;
• a second switch, comprising a first terminal for receiving the input signal, for connecting the input signal to a second terminal thereof during a second period;
• a first capacitor, comprising a first terminal coupled to the second terminal of the first switch, and a second terminal coupled to a first voltage, wherein the first capacitor is used for saving a first sample result of the input signal;
• a second capacitor, comprising a first terminal coupled to the second terminal of the second switch, and a second terminal thereof is coupled to a second voltage, wherein the second capacitor is used for saving a second sample result of the input signal;
• and
• an amplifier, comprising at least:
• a first positive input terminal, coupled to the second terminal of the first switch;
• a second positive input terminal, coupled to the second terminal of the second switch;
• a negative input terminal, for providing a reference input relative to inputs of the first positive input terminal and the second positive input terminal;
• an output terminal, for outputting the output signal;
• a first input stage, including a first input circuit coupled to the first positive input terminal, a second input circuit coupled to the second positive input terminal and a third input circuit coupled to the negative input terminal, wherein the first input circuit is disabled and the second input circuit is enabled during the first period, while the first input circuit is enabled and the second input circuit is disabled during the second period;
• a second input stage, including a fourth input circuit coupled to the first positive input terminal, a fifth input circuit coupled to the second positive input terminal and a sixth input circuit coupled to the negative input terminal, wherein the fourth input circuit is disabled and the fifth input circuit is enabled during the first period, while the fourth input circuit is enabled and the fifth input circuit is disabled during the second period;
• an output stage, for providing the output signal to the output terminal according to outputs of the first input circuit, the second input circuit and the third input circuit;
• a first clock signal attenuator, coupled to the first input circuit used for attenuating a second control signal and outputting the attenuated second control signal to the first input circuit, so as to disable the first input circuit during the first period and to enable the first input circuit during the second period and
• a second clock signal attenuator, coupled to the second input circuit for attenuating a first control signal and outputting the attenuated first control signal to the second input circuit, so as to enable the second input circuit during the first period and to disable the second input circuit during the second period;
• a third clock signal attenuator, coupled to the fourth input circuit and used for attenuating a fourth control signal and outputting the attenuated fourth control signal to the fourth input circuit, so as to disable the fourth input circuit during the first period and to enable the fourth input circuit during the second period;
• and
• a fourth clock signal attenuator, coupled to the fifth input circuit and used for attenuating a third control signal and outputting the attenuated third control signal to the fifth input circuit, so as to enable the fifth input circuit during the first period and to disable the fifth input circuit during the second period.