Method and apparatus for power efficient and scalable memory interface

An apparatus comprising:

• a power supply to provide a first supply voltage;
• a first Positive-channel Metal Oxide Semiconductor (PMOS) switch, the first PMOS switch including a source to couple to the first supply voltage;
• a bias control to couple to a gate of the first PMOS switch;
• a first signal line;
• a second signal line;
• a portion of a transmitting device having an output and an inverted output;
• a second PMOS switch having a source to couple to a drain of the first PMOS switch, a gate input to couple to the output of the portion of the transmitting device, and a drain to couple to the first signal line;
• a third PMOS switch having a source to couple to the drain of the first PMOS switch, a gate input to couple to the inverted output of the portion of the transmitting device, and a drain to couple to the second signal line;
• a first resistor to terminate the first signal line with reference to ground;
• a second resistor to terminate the second signal line with reference to ground;
• a fourth PMOS switch, the fourth PMOS switch including a source to couple to the power source to receive a second supply voltage;
• a second bias control to couple to a gate of the fourth PMOS switch;
• a portion of a receiving device;
• a first active load having a source to couple to ground, a gate input to couple to the second supply voltage and a drain to couple to the portion of the receiving device;
• a second active load having a source to couple to ground, a gate input to couple to the second supply voltage and a drain to couple to the portion of the receiving device;
• a fifth PMOS switch having a source to couple to a drain of the fourth PMOS switch, a gate input to couple to the first signal line, and a drain to couple to the drain of the first active load;
• a sixth PMOS switch having a source to couple to the drain of the fourth PMOS switch, a gate input to couple to the second signal line, and a drain to couple to the drain of the second active load:
• a third resistor to terminate the first signal line with reference to ground;
• and
• a fourth resistor to terminate the second signal line with reference to ground, wherein the first, second, third, and fourth resistors decouple the first supply voltage from the second supply, and wherein the second supply voltage is greater than the first supply voltage.