Fast/slow state machine latch
AssigneeInternational Business Machines Corporation
InventorsRichard R. Bell, Wilson D. Skipwith, Sebastian T. Ventrone
Life of this patent
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Abstract
A fast/slow state machine latch is provided that generates fast and slow select signals for a single toggle, low power multiplexer circuit. In accordance with an embodiment of the present invention, the fast/slow state machine latch includes a first latch with a delayed output, a second latch with an undelayed output, an inverter for coupling the delayed output of the first latch to an input of the second latch, and an exclusive-OR (XOR) gate coupled to the delayed output of the first latch and a data input, an output of the XOR gate coupled to an input of the first latch. A method for incorporating low power multiplexer circuits into a circuit design with minimal input from a circuit designer is also provided.
Claims14
A state machine latch having a dual output to drive a select line of a multiplexer in an integrated circuit, comprising:
- a first latch with a delayed output;
- a second latch with an undelayed output;
- an inverter for coupling the delayed output of the first latch to an input of the second latch;
- and
- an exclusive-OR (XOR) gate coupled to the delayed output of the first latch and a data input, an output of the XOR gate coupled to an input of the first latch.
An integrated circuit, comprising:
- a low power multiplexer circuit;
- and
- a state machine latch for driving a select line of the low power multiplexer circuit, the state machine latch comprising:
- a first latch with a delayed output;
- a second latch with an undelayed output;
- an inverter for coupling the delayed output of the first latch to an input of the second latch;
- and
- an exclusive-OR (XOR) gate coupled to the delayed output of the first latch and a data input, an output of the XOR gate coupled to an input of the first latch.
Dependencies are inferred from the claim text.