Programmable logic devices with distributed memory

A programmable logic device comprising:

• a first means for providing programmable logic functions, wherein the first providing means is distributed within a first plurality of rows and does not provide distributed random access memory functions;
• a second means for providing programmable logic functions and distributed random access memory functions, wherein the second providing means is distributed within a second plurality of rows;
• and
• means for storing configuration data for configuring the first and second providing means,
• wherein there are at least twice as many rows of the first means than of the second means.

A programmable logic device comprising:

• a plurality of input/output blocks adapted to provide an input/output interface for the programmable logic device;
• a first plurality of logic blocks arranged in one or more rows, wherein each logic block includes two or more discrete lookup tables and is adapted to provide programmable logic functions but is not adapted to provide distributed random access memory functions;
• a second plurality of logic blocks arranged in one or more rows, wherein each logic block includes two or more discrete lookup tables and is adapted to provide programmable logic functions and is further adapted to provide distributed random access memory functions;
• one or more rows of embedded block RAM;
• a routing structure adapted to programmably interconnect the input/output blocks, the first and second plurality of logic blocks, and the embedded block RAM;
• and
• configuration memory cells adapted to store configuration data to configure the input/output blocks, the first and second plurality of logic blocks, the embedded block RAM, and the routing structure.