US 7,459,930 B2Granted

Digital calibration circuits, devices and systems including same, and methods of operation

AssigneeMicron Technology, Inc.

InventorShizhong Mei

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Abstract

A calibration circuit for matching the output impedance of a driver by calibrating adjustments to the driver is described. The calibration circuit includes a driver circuit with a plurality of calibration transistors configured to receive a plurality of adjustment signals. The calibration circuit also includes a comparator circuit, and a binary searcher. The driver provides a signal corresponding to an output impedance to the comparator circuit. The output impedance signal is compared to a target impedance, and the comparator circuit then provides logic signals to the binary searcher representing whether the output impedance is greater than the target impedance. The binary searcher then selects a type of step size and count direction, in response to the logic signals, to count the number of steps for adjusting the calibration transistors of the driver.

Claims51

Dependent claims

A calibration circuit comprising:

a driver circuit having a plurality of calibration transistors configured to receive a plurality of adjustment signals, the driver circuit operable to generate a first output signal having a value corresponding to the plurality of adjustment signals;
a comparator circuit coupled to the driver circuit to receive the first output signal, the comparator circuit operable to generate a first control signal determined by the difference between the value of the first output signal and a predetermined value, and the comparator circuit further operable to generate a second control signal determined by whether the first output signal is greater than the predetermined value, the comparator circuit comprising:
a first comparator configured to compare the first output signal to a value above the predetermined value;
a second comparator configured to compare the first output signal to a value below the predetermined value;
and
a third comparator configured to compare the first output signal to the predetermined value;
and
a binary searcher coupled to receive the first and second control signals from the comparator circuit, and operable to select either a relatively larger binary step count or a relatively smaller binary step count in response to the first control signal and determine the upwards or downwards direction of the selected binary step count in response to the second control signal, the binary searcher further operable to adjust the plurality of calibration transistors in accordance with the selected binary step count and in the selected direction of the count.

5 more elements

An output driver impedance calibration circuit comprising:

a driver having a plurality of transistors, the driver configured to receive a plurality of adjustment signals, the driver being operable to select a subset of transistors in response to the plurality of adjustment signals and to generate a signal corresponding to an adjusted output impedance based on the subset of transistors that are selected;
a comparator circuit configured to receive the signal corresponding to the adjusted output impedance and a signal corresponding to a target impedance, the comparator circuit operable to compare the received driver and target impedance signals to generate a set of logic signals from which the difference in magnitude between the adjusted output impedance and the target impedance can be determined;
a filtering circuit coupled to receive the set of logic signals from the comparator circuit, and operable to generate a first adjustment control signal indicative of whether the difference between the adjusted output impedance and the target impedance is greater than a predetermined value, and further operable to generate a second adjustment control signal indicative of whether the output impedance is greater than the target impedance;
and
a binary searcher coupled to receive the first and second adjustment control signals, and operable to select either a relatively larger adjustment step size or a relatively smaller adjustment step size in response to the first adjustment control signal and operable to select a step count in the upward or downward direction in response to the second adjustment control signal, the binary searcher further operable to provide the plurality of adjustment signals to the driver in accordance with the selected adjustment step size and step count.

2 more elements

A memory device, comprising:

an address bus;
a control bus;
a data bus;
an address decoder coupled to the address bus;
a read/write circuit coupled to the control bus;
an array of memory cells coupled to the address decoder, control circuit, and read/write circuit;
an output driver circuit for outputting data read from the array of memory cells;
and
a calibration circuit for a driver comprising:
a driver circuit having a plurality of calibration transistors configured to receive a plurality of adjustment signals, the driver circuit operable to generate a first output signal having a value corresponding to the plurality of adjustment signals;
a comparator circuit coupled to the driver circuit to receive the first output signal, the comparator circuit operable to generate a first control signal determined by the difference between the value of the first output signal and a predetermined value, and the comparator circuit further operable to generate a second control signal determined by whether the first output signal is greater than the predetermined value, the comparator circuit comprising:
a first comparator configured to compare the first output signal to a value above the predetermined value;
a second comparator configured to compare the first output signal to a value below the predetermined value;
and
a third comparator configured to compare the first output signal to the predetermined value;
and
a binary searcher coupled to receive the first and second control signals from the comparator circuit, and operable to select either a relatively larger binary step count or a relatively smaller binary step count in response to the first control signal and determine the upwards or downwards direction of the selected binary step count in response to the second control signal, the binary searcher further operable to adjust the plurality of calibration transistors in accordance with the selected binary step count and in the selected direction of the count.

14 more elements

A memory device, comprising:

an address bus;
a control bus;
a data bus;
an address decoder coupled to the address bus;
a read/write circuit coupled to the control bus;
an array of memory cells coupled to the address decoder, control circuit, and read/write circuit;
an output driver circuit for outputting data read from the array of memory cells;
and
an output driver impedance calibration circuit comprising:
a driver having a plurality of transistors, the driver configured to receive a plurality of adjustment signals, the driver being operable to select a subset of transistors in response to the plurality of adjustment signals and generate a signal corresponding to an adjusted output impedance based on the subset of transistors that are selected;
a comparator circuit configured to receive the signal corresponding to the adjusted output impedance and a signal corresponding to a target impedance, the comparator circuit operable to compare the received driver and target impedance signals to generate a set of logic signals from which the difference in magnitude between the adjusted output impedance and the target impedance can be determined;
a filtering circuit coupled to receive the set of logic signals from the comparator circuit, and operable to generate a first adjustment control signal indicative of whether the difference between the adjusted output impedance and the target impedance is greater than a predetermined value, and further operable to generate a second adjustment control signal indicative of whether the output impedance is greater than the target impedance;
and
a binary searcher coupled to receive the first and second adjustment control signals, and operable to select either a relatively larger adjustment step size or a relatively smaller adjustment step size in response to the first adjustment control signal and operable to select a step count in the upward or downward direction in response to the second adjustment control signal, the binary searcher further operable to provide the plurality of adjustment signals to the driver in accordance with the selected adjustment step size and step count.

11 more elements

A computer system, comprising:

a data input device;
a data output device;
a processor coupled to the data input and output devices;
and
a memory device coupled to the processor, the memory device comprising:
an address bus;
a control bus;
a data bus;
an address decoder coupled to the address bus;
a read/write circuit coupled to the control bus;
an array of memory cells coupled to the address decoder, control circuit, and read/write circuit;
an output driver circuit for outputting data read from the array of memory cells;
and
a calibration circuit for a driver comprising:
a driver circuit having a plurality of calibration transistors configured to receive a plurality of adjustment signals, the driver circuit operable to generate a first output signal having a value corresponding to the plurality of adjustment signals;
a comparator circuit coupled to the driver circuit to receive the first output signal, the comparator circuit operable to generate a first control signal determined by the difference between the value of the first output signal and a predetermined value, and the comparator circuit further operable to generate a second control signal determined by whether the first output signal is greater than the predetermined value, the comparator circuit comprising:
a first comparator configured to compare the first output signal to a value above the predetermined value;
a second comparator configured to compare the first output signal to a value below the predetermined value;
and
a third comparator configured to compare the first output signal to the predetermined value;
and
a binary searcher coupled to receive the first and second control signals from the comparator circuit, and operable to select either a relatively larger binary step count or a relatively smaller binary step count in response to the first control signal and determine the upwards or downwards direction of the selected binary step count in response to the second control signal, the binary searcher further operable to adjust the plurality of calibration transistors in accordance with the selected binary step count and in the selected direction of the count.

19 more elements

A computer system, comprising:

a data input device;
a data output device;
a processor coupled to the data input and output devices;
and
a memory device coupled to the processor, the memory device comprising:
an address bus;
a control bus;
a data bus;
an address decoder coupled to the address bus;
a read/write circuit coupled to the control bus;
an array of memory cells coupled to the address decoder, control circuit, and read/write circuit;
an output driver circuit for outputting data read from the array of memory cells;
and
an output driver impedance calibration circuit comprising:
a driver having a plurality of transistors, the driver configured to receive a plurality of adjustment signals, the driver being operable to select a subset of transistors in response to the plurality of adjustment signals and generate a signal corresponding to an adjusted output impedance based on the subset of transistors that are selected;
a comparator circuit configured to receive the signal corresponding to the adjusted output impedance and a signal corresponding to a target impedance, the comparator circuit operable to compare the received driver and target impedance signals to generate a set of logic signals from which the difference in magnitude between the adjusted output impedance and the target impedance can be determined;
a filtering circuit coupled to receive the set of logic signals from the comparator circuit, and operable to generate a first adjustment control signal indicative of whether the difference between the adjusted output impedance and the target impedance is greater than a predetermined value, and further operable to generate a second adjustment control signal indicative of whether the output impedance is greater than the target impedance;
and
a binary searcher coupled to receive the first and second adjustment control signals, and operable to select either a relatively larger adjustment step size or a relatively smaller adjustment step size in response to the first adjustment control signal and operable to select a step count in the upward or downward direction in response to the second adjustment control signal, the binary searcher further operable to provide the plurality of adjustment signals to the driver in accordance with the selected adjustment step size and step count.

16 more elements

Dependencies are inferred from the claim text.

Facts

Application: 11/599,889Filed 14 Nov 2006
Published: US 2008/0112246 A115 May 2008
Granted: 2 Dec 2008
Term ends: Not estimatedThe source records don’t support an estimate.

Classification11 codes

G11C 7/1051
Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers: data output circuits, e.g. read-out amplifiers,…
G11C 7/1069
Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits: i/O lines read…
G11C 11/4093
Read-write [R-W] circuits: input/output [I/O] data interface arrangements, e.g. data buffers
G11C 29/02
Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation: detection or location of defective…