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US 7,459,929 B2Granted
Semiconductor integrated circuit device and on-die termination circuit
AssigneeSamsung Electronics Co., Ltd.
InventorIn-Young Chung
Life of this patent
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Abstract
The present invention discloses a semiconductor integrated circuit device and an on-die termination circuit. The circuit includes a level shifter for boosting an on-die termination control signal to a high voltage level; and a first NMOS transistor connected between a power voltage and a pad and terminating the pad to a first termination voltage level in response to the high voltage level. The on-die termination circuit has a reduced input capacitance.
Claims4
An on-die termination circuit responsive to an on-die termination control signal, the circuit comprising:
- an input pad;
- a level shifter for boosting the on-die termination control signal to a high voltage level control signal;
- a power voltage;
- a first NMOS transistor connected between the power voltage and the input pad and being activated by the high voltage level control signal;
- and
- a second NMOS transistor connected between a ground voltage and the input pad and being activated by the on-die termination control signal,
- wherein the input pad is terminated to a particular termination voltage level when the first NMOS transistor and the second NMOS transistor are simultaneously activated.
4 more elements
A semiconductor integrated circuit device, comprising:
- a control signal generating portion for generating an on-die termination control signal in response to a command applied from an external portion;
- and
- an on-die termination circuit including a level shifter for boosting the on-die termination control signal to a boosted high voltage level control signal, a power voltage source, a pad, and a first NMOS transistor connected between the power voltage source and the pad, the NMOS transistor being controlled by the boosted high voltage level control signal, wherein the on-die termination circuit further includes a second NMOS transistor connected between ground voltage and the pad, and the pad is terminated to a particular termination voltage level when the first NMOS transistor and the second NMOS transistor are simultaneously activated.
Dependencies are inferred from the claim text.