US 7,459,927 B2Granted

Superconductive crossbar switch

OwnerFernand D. Bedardinventor

Life of this patent

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Abstract

A superconductor crossbar switch for connecting a plurality of inputs with a plurality of outputs, including a switching cell having an input, an output and a circuit for connecting the input with the output for bidirectionally transmitting data therebetween. The connection of the retaining and releasing circuitry of a plurality of cells enables the switch to simultaneously retain a selected cell or cells of a group of cells and disable the remaining cells of that group, whereby a subsequent query on a disabled cell is inoperative until the selected cell or cells is released. The crossbar switch is characterized by latency on the order of nanoseconds, a data rate per channel on the order of gigabits per second, essentially zero crosstalk, and detection of contention in nanoseconds or less and resolution of contention in nanoseconds or less.

Claims1

Dependent claims

A superconducting crossbar switch, comprising:

a plurality of input lines;
a matrix of a plurality of cells, each of the plurality of cells being coupled to one of the plurality of input lines, wherein each of the plurality of cells includes:
at least one first circuit portion containing at least one first superconducting switch;
and
at least one second circuit portion, wherein at least one first signal via the at least one second circuit portion triggers the at least one first superconducting switch;
a plurality of output lines, each of the plurality of output lines coupled to at least one of the plurality of cells;
at least one first processor glue chip and at least one second processor glue chip coupled to the matrix of the plurality of cells;
at least one first memory glue chip and at least one second memory glue chip coupled to the matrix of the plurality of cells;
at least one first plurality of processors coupled to the at least one first glue chip via at least one first input data line;
at least one second plurality of processors coupled to the at least one second glue chip;
at least one first plurality of memory devices coupled to the at least one first memory glue chip;
and
at least one second plurality of memory devices coupled to the at least one second memory glue chip.

10 more elements

Dependencies are inferred from the claim text.

Facts

Application: 11/209,662Filed 24 Aug 2005 · continuation
Priority: 23 Jul 2001
Published: US 2007/0236245 A111 Oct 2007
Granted: 2 Dec 2008
Term ends: Not estimatedThe source records don’t support an estimate.

Classification10 codes

H03K 17/92
Characterised by the components used: by the use, as active elements, of superconductive devices
H04Q 3/0004
Selecting arrangements: using crossbar selectors in the switching stages
H04Q 3/521
Using static devices in switching stages, e.g. electronic switching arrangements: using semiconductors in the switching stages
H04Q 2213/1302
Indexing scheme relating to selecting arrangements in general and for multiplex systems: relay switches

Family

Application60/306,880Us provisional application · filed 23 Jul 2001
Application10/200,115Parent of this continuation · filed 23 Jul 2002
US 2007/0236245 A1Pre-grant publication · published 11 Oct 2007
US 6,960,929 B2Parent of this continuation
US 2003/0054960 A1Published application
US 7,459,927 B2This patent

From the US filing history. Foreign family members aren’t listed.