Soft-start circuit and method for low-dropout voltage regulators

A low drop-out voltage regulator, comprising:

• a power FET connected by a source and a drain between an input node for receiving an input voltage and an output node for providing an output voltage;
• a feedback loop configured to compare a voltage representing the output voltage to a first reference voltage and provide an output signal representing the difference between them to a gate of the power FET;
• a controllable sense resistor having a first terminal connected to the input node;
• a sense FET connected by a source and a drain between a second terminal of the controllable sense resistor and the output node, and connected to receive at a gate the output signal of the feedback loop;
• a current limit amplifier having a first input connected to the connection node of the controllable sense resistor and the sense FET and a second input connected to receive a second reference voltage representing a current limit, and having an output for providing an output signal when the voltage at the connection node of the controllable sense resistor and the sense FET goes below the second reference voltage;
• a limit FET connected by a source and a drain between the input node and the output of the feedback loop and having a gate connected to the output of the current limit amplifier;
• and
• a control unit adapted to provide, at start-up, a control signal to the controllable resistor to cause the resistance value of the controllable resistor to decrease over a predetermined time to a final value.