Stiffener for flip chip BGA package

A semiconductor device package, comprising:

• a package substrate;
• a flip chip die coupled to the package substrate;
• a stiffener made from a graphite material, coupled to the package substrate, and having a recess region to accommodate the die and four sides positioned laterally around the die so that a surface of the die is exposed through the recess region, wherein the stiffener is composed of a material having a first CTE value;
• and
• a separate thermally conductive heat spreader having a second CTE value which is higher than the first CTE value and attached to the stiffener and the exposed surface of the die.

A semiconductor device package, comprising:

• a package substrate;
• a flip chip die coupled to the package substrate;
• a graphite stiffener, coupled to the package substrate, and having a recess region to accommodate the die and four sides positioned laterally around the die so that a surface of the die is exposed through the recess region, wherein the stiffener is composed of a material having a CTE value less than 12 ppm/° C. and a thermal conductivity value greater than 300 W/mK;
• and
• a separate thermally conductive heat spreader in contact with the die and the four sides of the stiffener and having a CTE value greater than the stiffener.

A method for packaging a semiconductor device, comprising:

• providing a package substrate;
• coupling a flip chip die to the package substrate;
• coupling a graphite stiffener to the package substrate having a recess region to accommodate the die and four sides around the periphery of the die so that a surface of the die is exposed through the recess region, wherein the stiffener is positioned laterally around the die within the recess region and composed of a material having a CTE value sufficient to absorb or redistribute stresses caused by thermal mismatches between the die and the substrate;
• and
• coupling a separate thermally conductive heat spreader having a second CTE value greater than the first CTE value to the stiffener and the exposed surface of the die.

A method for packaging a semiconductor device, comprising:

• providing a package substrate, wherein the package substrate includes a core with a thickness between 800 and 1000 microns;
• coupling a flip chip die to the package substrate;
• coupling a graphite stiffener to the package substrate, wherein the stiffener is positioned laterally around the die so that a surface of the die is exposed and composed of a material having a CTE value less than 12 ppm/° C.;
• and
• coupling a separate thermally conductive heat spreader to the stiffener and the exposed surface of the die, wherein the heat spreader has a CTE value greater than the stiffener.

A semiconductor device package, comprising:

• a package substrate, wherein the package substrate includes a core with a thickness between 800 and 1000 microns;
• a flip chip die coupled to the package substrate;
• and
• a graphite stiffener positioned laterally around the die so that a surface of the die is exposed, the stiffener having a CTE sufficient for substantially controlling the co-planarity of the semiconductor device package.