Lead frame structure having blocking surfaces and semiconductor package integrated with the lead frame structure

A semiconductor package integrated with a lead frame structure, comprising:

• a lead frame comprising a separated die pad and a plurality of leads formed around the die pad, the die pad comprising a first mounting portion and a second mounting portion separated from the first mounting portion by a gap, wherein each of the first and second mounting portions has a blocking surface comprised of a plurality of stepped surfaces to taper the gap bordering the gap, and the blocking surface of the first mounting portion corresponds to the blocking surface of the second mounting portion;
• a first chip and a second chip, the first chip being mounted to the first and second mounting portions and on a top surface of the lead frame, and the second chip being mounted to the first and second mounting portions and on a bottom surface of the lead frame, wherein the first and second chips are electrically connected to the leads via bonding wires;
• and
• an encapsulant formed of an encapsulating resin, for encapsulating he die pad, the first chip, the second chip, and a portion of the leads, wherein a flow rate of the encapsulating resin flowing through the gap during formation of the encapsulant is reduced by the blocking surfaces.