Insulated gate semiconductor device with small feedback capacitance and manufacturing method thereof
AssigneeKabushiki Kaisha Toshiba
InventorKoichi Sugiyama
Life of this patent
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Abstract
Disclosed is an insulated gate semiconductor device including a first region having a gate electrode region and a first insulating film region surrounding the gate electrode region; a semiconductor region which includes a channel forming region and is disposed to oppose the gate electrode region with the first insulating film region between them; and a second region which has a conductor region buried in a semiconductor region not including the channel forming region disposed to oppose the gate electrode region with the first insulating film region between them, and has a second insulating film region which separates the conductor region from the semiconductor region.
Claims14
An insulated gate semiconductor device, comprising:
- a first region having a gate electrode region and a first insulating film region surrounding the gate electrode region;
- a semiconductor region including a channel forming region and provided to oppose the gate electrode region with the first insulating film region between the semiconductor region and the gate electrode region;
- and
- a second region buried in the semiconductor region so as to reach a vertical position deeper than the first region and being adjacent to and in contact with the first region, the second region having a conductor region and a second insulating film region to separate the conductor region from the semiconductor region,
- wherein the first region is buried in first groove-like removed portions of the semiconductor region;
- and
- wherein the second region is buried in second groove-like removed portions of the semiconductor region, and provided to oppose at least the channel forming region of the semiconductor region through the first region.
An insulated gate semiconductor device, comprising:
- a first region having a gate electrode region and a first insulating film region surrounding the gate electrode region;
- a semiconductor region including a channel forming region and provided to oppose the gate electrode region with the first insulating film region between the semiconductor region and the gate electrode region;
- and
- a second region buried in the semiconductor region so as to reach a vertical position deeper than the first region and being adjacent to and in contact with the first region, the second region having a conductor region and a second insulating film region to separate the conductor region from the semiconductor region,
- wherein the second region is positioned between the first region and the semiconductor region so as to be in contact with the first region and the semiconductor region.
An insulated gate semiconductor device, comprising:
- a first region having a gate electrode region and a first insulating film region surrounding the gate electrode region;
- a semiconductor region including a channel forming region and an emitter region adjacent to the channel forming region, the semiconductor region being provided to oppose the gate electrode region with the first insulating film region between the semiconductor region and the gate electrode region;
- and
- a second region buried in the semiconductor region so as to reach a vertical position deeper than the first region and being adjacent to and in contact with the first region, the second region having a conductor region and a second insulating film region to separate the conductor region from the semiconductor region, the second insulating film region being in contact with the semiconductor region, the conductor region being configured so as to have a same voltage as the emitter region,
- wherein the insulated gate semiconductor device is an IGBT.
Dependencies are inferred from the claim text.