Integrated DRAM-NVRAM multi-level memory

An integrated DRAM-NVRAM memory cell comprising:

• a silicon-on-insulator substrate comprising a layer of insulating material and a plurality of pillars formed in silicon on the insulator;
• a drain region formed in the top of each pillar;
• a source region formed at the bottom of each pillar;
• a vertical gate formed along a side wall of a first pillar;
• a trapping layer formed along an opposite side wall of the first pillar;
• and
• a vertical control gate formed over the trapping layer such that the vertical control gate is shared by an adjacent NVRAM transistor.

An integrated DRAM-NVRAM memory cell array comprising:

• a silicon substrate comprising a plurality of pillars that form a trench between each pair of pillars;
• a drain region formed in the top of each pillar;
• a source region formed at the bottom of each trench;
• a first vertical gate formed along an outside side wall of a first pillar wherein only an insulator separates the first vertical gate from the side wall;
• a second vertical gate formed along an outside side wall of a second pillar wherein only an insulator separates the second vertical gate from the side wall;
• first and second trapping layers respectively formed along each opposing side wall of a trench formed between the first and second pillars;
• and
• a vertical control gate formed in the trench and over the first and second trapping layers wherein the vertical control gate is shared by adjacent NVRAM memory cells formed in the trench.