Active matrix display and electrooptical device

A display device comprising:

• a source line formed over a substrate;
• a gate line formed over the substrate extending across the source line;
• and
• a pixel formed over the substrate at an intersection of the source line and the gate line, the pixel comprising:
• at least first and second thin film transistors wherein a source or drain of the first thin film transistor is electrically connected to the source line;
• a pixel electrode electrically connected to a source or drain of the second thin film transistor wherein the pixel electrode is electrically connected to the source line through at least the first and second thin film transistors;
• and
• wherein a portion of the source line covers said first thin film transistor so that the first transistor is light shielded while both of (1) the source or drain of the second thin film transistor which is electrically connected to the pixel electrode and (2) a channel of the second thin film transistor, are not covered by any portion of the source line, and
• wherein a width of the source line is larger than a width of the channel region of the first thin film transistor, the width of the channel region taken along a direction perpendicular to a current flow direction of said channel region, and
• wherein the pixel electrode does not overlap the source line.

A display device comprising:

• a source line formed over a substrate wherein the source line extends along a first direction;
• a gate line formed over the substrate extending along a second direction orthogonal to the first direction;
• and
• a pixel formed over the substrate at an intersection of the source line and the gate line, the pixel comprising:
• a semiconductor layer including a first channel region of a first thin film transistor and a second channel region of a second thin film transistor;
• a pixel electrode electrically connected to the source line through at least the first and second thin film transistors;
• wherein the semiconductor layer intersects the gate line at first and second intersecting portions wherein the first channel region corresponds to a first intersecting portion between the semiconductor layer and the gate line and the second channel region corresponds to the second intersecting portion between the semiconductor layer and the gate line;
• wherein the source line covers the first intersecting portion while the source line does not cover the second intersecting portion;
• wherein a current flow direction in the first and second channel regions is in parallel with the first direction;
• and
• wherein a width of the source line is larger than a width of the first channel region, the width of the first channel region taken along a direction perpendicular to the current flow direction.