Methods of forming dual-damascene interconnect structures using adhesion layers having high internal compressive stresses

A method of forming a dual-damascene copper wiring pattern, comprising the steps of:

• forming a first copper wiring pattern on a semiconductor substrate;
• forming an electrically insulating capping layer on the first copper wiring pattern;
• forming an electrically insulating adhesion layer having an internal compressive stress of greater than about 100 MPa, on the electrically insulating capping layer, by depositing a silicon dioxide adhesion layer using source gases containing octamethylcyclotetrasilane (OMCTS) and helium (He);
• forming an inter-metal dielectric layer on the electrically insulating adhesion layer;
• forming an opening that extends through the inter-metal dielectric layer, the electrically insulating adhesion layer and the electrically insulating capping layer and exposes the first copper wiring pattern;
• and
• forming a second copper wiring pattern in the opening.

A method of forming a dual-damascene copper wiring pattern, comprising the steps of:

• forming a first dielectric layer comprising SIOCH on a semiconductor substrate;
• forming a first copper wiring pattern on the first dielectric layer;
• forming an electrically insulating capping layer comprising SiCN on the first copper wiring pattern;
• depositing a silicon dioxide adhesion layer on the electrically insulating capping layer, using a first source gas containing octamethylcyclotetrasilane (OMCTS) at a volumetric flow rate in a range from about 500 sccm to about 700sccm and a second source gas containing helium at a volumetric flow rate in a range from about 1000 sccm to about 3000 sccm;
• forming a second dielectric layer comprising SiCOH on the silicon dioxide adhesion layer;
• forming an opening that extends through the second dielectric layer, the silicon dioxide adhesion layer and the electrically insulating capping layer and exposes the first copper wiring pattern;
• and
• forming a second copper wiring pattern in the opening.

A method of forming an electrical interconnect structure, comprising the steps of:

• forming a dielectric layer on a semiconductor substrate;
• forming a metal wiring pattern on the dielectric layer;
• and
• depositing an adhesion layer on the metal wiring pattern using a first source gas containing octamethylcyclotetrasilane (OMCTS) at a volumetric flow rate in a range from about 500 sccm to about 700 sccm and a second gas containing helium at a volumetric flow rate in a range from about 1000 sccm to about 3000 sccm.