Preventing cavitation in high aspect ratio dielectric regions of semiconductor device
AssigneeInternational Business Machines Corporation
InventorsPaul D. Agnello, Rajeev Malik, K. Paul Muller
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Abstract
Methods for preventing cavitation in high aspect ratio dielectric regions in a semiconductor device, and the device so formed, are disclosed. The invention includes depositing a first dielectric in the high aspect ratio dielectric region between a pair of structures, and then removing the first dielectric to form a bearing surface adjacent each structure. The bearing surface prevents cavitation of the interlayer dielectric that subsequently fills the high aspect ratio region.
Claims15
A method of preventing interlayer dielectric cavitation between a pair of structures having a high aspect ratio region therebetween in a semiconductor device, the method comprising:
- depositing a first dielectric in the high aspect ratio region;
- removing the first dielectric to form a bearing surface adjacent each structure, wherein the bearing surface is inclined to a spacer of each structure and extends continuously upwards from a surface coplanar with the base of each structure terminating at a first portion along the height of the spacer of each structure and wherein the remaining first dielectric of the bearing surface partially fills an undercut of each structure;
- depositing a barrier layer over each structure including respective bearing surfaces, a second portion along the height of the spacer of each structure, and the high aspect ratio region between the structures;
- and
- filling the high aspect ratio region with an interlayer dielectric after the depositing of the barrier layer.
A method for preventing a contact short between a pair of gate structures having a high aspect ratio region therebetween in a semiconductor device, the method comprising the steps of:
- depositing a first dielectric in the high aspect ratio region;
- removing the first dielectric to form a bearing surface adjacent each gate structure, wherein the bearing surface is inclined to a spacer of each gate structure and extends continuously upwards from a surface coplanar with the base of each gate structure terminating at a first portion along the height of the spacer of each gate structure, each gate structure being elevated above a source-drain region of the semiconductor device such that the bearing surface extends vertically beyond the base of each gate structure towards the source-drain region;
- depositing a barrier layer over each gate structure including respective bearing surfaces, a second portion along the height of the spacer of each structure, and the high aspect ratio region between the gate structures;
- filling the high aspect ratio region with an interlayer dielectric after the depositing of the barrier layer;
- and
- forming a contact through the interlayer dielectric between the gate structures
- wherein the high aspect ratio region includes a constrictive region having a constrictive portion and a lower portion, the lower portion having a substantially horizontal dimension greater than the constrictive portion, and wherein the bearing surface fills the lower portion of the constrictive region.
Dependencies are inferred from the claim text.