Integrated circuits and interconnect structure for integrated circuits
AssigneeMarvell World Trade Ltd.
InventorSehat Sutardja
Life of this patent
Estimating the term…
Abstract
A method for reducing parasitic resistance in an integrated circuit, comprises connecting first and second terminals of a first transistor to second and first plane-like metal layers, respectively; connecting third and fourth terminals of a second transistor to said first and a third plane-like metal layer, respectively; and connecting first, second and third contact portions of a fourth plane-like metal layer to said second plane-like metal layer, said first plane-like metal layer and said third plane-like metal layer, respectively.
Claims44
A method for reducing parasitic resistance in an integrated circuit, comprising:
- connecting first and second terminals of a first transistor to second and first plane-like metal layers, respectively;
- connecting third and fourth terminals of a second transistor to said first and a third plane-like metal layer, respectively;
- and
- connecting first, second and third contact portions of a fourth plane-like metal layer to said second plane-like metal layer, said first plane-like metal layer and said third plane-like metal layer, respectively
- wherein said first, second, and third contact portions are located at an exposed upper surface of the fourth plane-like metal layer.
A method for reducing parasitic resistance in an integrated circuit, comprising:
- connecting first and second terminals of a first transistor to second and first plane-like metal layers, respectively;
- connecting third and fourth terminals of a second transistor to said first and a third plane-like metal layer, respectively;
- and
- connecting first, second and third contact portions of a fourth plane-like metal layer to said second plane-like metal layer, said first plane-like metal layer and said third plane-like metal layer, respectively,
- wherein said first and second transistors are NMOS transistors, said first and third terminals are drains and said second and fourth terminals are sources.
A method for reducing parasitic resistance in an integrated circuit, comprising:
- connecting first and second terminals of a first transistor to second and first plane-like metal layers, respectively;
- connecting third and fourth terminals of a second transistor to said first and a third plane-like metal layer, respectively;
- connecting first, second and third contact portions of a fourth plane-like metal layer to said second plane-like metal layer, said first plane-like metal layer and said third plane-like metal layer, respectively;
- and
- arranging said first plane-like metal layer between said second and third plane-like metal layers and said first and second transistors.
A method for reducing parasitic resistance in an integrated circuit, comprising:
- connecting first and second terminals of a first transistor to second and first plane-like metal layers, respectively;
- connecting third and fourth terminals of a second transistor to said first and a third plane-like metal layer, respectively;
- connecting first, second and third contact portions of a fourth plane-like metal layer to said second plane-like metal layer, said first plane-like metal layer and said third plane-like metal layer, respectively;
- and
- connecting first, second and third transmission lines of a leadframe to said first, second and third contact portions, respectively,
- wherein said leadframe and said integrated circuit implement a quad flat no-lead (QFN) package.
Dependencies are inferred from the claim text.