Back to results
US 7,458,821 B2Granted
Electrical interface for memory connector
AssigneeIntel Corporation
InventorsDan Willis, David Kraus
Life of this patent
Estimating the term…
Abstract
According to some embodiments, a connector to receive a memory module includes a first row of a first plurality of interconnect ends, a second row of a second plurality of interconnect ends adjacent to the first row, and a third row of a third plurality of interconnect ends adjacent to the second row. An interconnect end of the first plurality of interconnect ends, an interconnect end of the second plurality of interconnect ends, and an interconnect end of the third plurality of interconnect ends may be substantially aligned.
Claims19
A system comprising:
- a double data rate dual in-line memory module;
- and
- a connector holding the memory module, the connector comprising:
- a first row of connectors;
- a first row of a first plurality of interconnect ends adjacent to a first side of the first row of connectors;
- a second row of a second plurality of interconnect ends adjacent to a second side of the first row of connectors;
- a third row of a third plurality of interconnect ends adjacent to the second row of a second plurality of interconnect ends,
- a second row of connectors;
- a fourth row of a fourth plurality of interconnect ends adjacent to the third row of a third plurality of interconnect ends and adjacent to a first side of the second row of connectors;
- and
- a fifth row of a fifth plurality of interconnect ends adjacent to the fourth row of a fourth plurality of interconnect ends and adjacent to a second side of the second row of connectors,
- wherein a first interconnect end of the first plurality of interconnect ends is coupled to a first connector of the first row of connectors, wherein a first interconnect end of the second plurality of interconnect ends is coupled to a second connector of the first row of connectors, wherein a first interconnect end of the third plurality of interconnect ends is coupled to a third connector of the first row of connectors and is coupled to a third connector of the second row of connectors, wherein a first interconnect end of the fourth plurality of interconnect ends is coupled to a first connector of the second row of connectors, and wherein a first interconnect end of the fifth plurality of interconnect ends is coupled to a second connector of the second row of connectors.
9 more elements
An electrical interface to receive a memory module, comprising:
- a first row of connectors;
- a first row of a first plurality of interconnect ends adjacent to a first side of the first row of connectors;
- a second row of a second plurality of interconnect ends adjacent to a second side of the first row of connectors;
- a third row of a third plurality of interconnect ends adjacent to the second row of a second plurality of interconnect ends;
- a second row of connectors;
- a fourth row of a fourth plurality of interconnect ends adjacent to the third row of a third plurality of interconnect ends and adjacent to a first side of the second row of connectors;
- and
- a fifth row of a fifth plurality of interconnect ends adjacent to the fourth row of a fourth plurality of interconnect ends and adjacent to a second side of the second row of connectors,
- wherein first interconnect end of the first plurality of interconnect ends is coupled to a first connector of the first row of connectors, wherein a first interconnect end of the second plurality of interconnect ends is coupled to a second connector of the first row of connectors, wherein a first interconnect end of the third plurality of interconnect ends is coupled to a third connector of the first row of connectors and is coupled to a third connector of the second row of connectors, wherein a first interconnect end of the fourth plurality of interconnect ends is coupled to a first connector of the second row of connectors, and wherein a first interconnect end of the fifth plurality of interconnect ends is coupled to a second connector of the second row of connectors.
6 more elements
Dependencies are inferred from the claim text.