Memory device and method of operating the same

A memory device comprising:

• a local input/output line pair configured to be coupled to a memory cell and a bit line pair through a first switching circuit;
• a global input/output line pair configured to be coupled to the local input/output line pair through a second switching circuit;
• a precharge circuit configured to precharge the global input/output line pair to a predetermined voltage level;
• a sense amplifier configured to detect and amplify a potential difference between the global input/output line pair;
• a control signal generating unit configured to generate a first switching control signal, a second switching control signal, a precharge circuit control signal and a sense amplifier control signal in response to a read command;
• and
• a detect control signal generating unit coupled to the control signal generating unit, configured to generate a detection precharge control signal for controlling an operation of the precharge circuit and a detection sense amplifier control signal, separate and distinct from the detection precharge control signal, for controlling an operation of the sense amplifier based on the detected potential difference between the global input/output line pair.

A method of operating a memory device having a memory cell, a local input/output line pair and a global input/output line pair configured for data transfer, the method comprising:

• generating a plurality of control signals based on a read command;
• enabling a sense amplifier coupled to the global input/output line pair in response to at least one of the control signals;
• generating a detect signal based upon detecting a potential difference between the global input/output line pair;
• and
• generating a detection sense amplifier control signal and disabling the sense amplifier in response to the detect signal, and generating a detection precharge control signal, which is separate and distinct from the detection sense amplifier control signal, and precharging the global input/output line pair to a predetermined voltage level in response to the detect signal.

A memory device having a memory cell, a local input/output line pair and a global input/output line pair configured for data transfer, the memory device comprising:

• a sense amplifier configured to detect and amplify a potential difference between the global input/output line pair;
• a detecting unit configured to generate a detect signal based on a detection of the potential difference between the global input/output line pair;
• a precharge circuit configured to precharge the global input/output line pair to a predetermined voltage level;
• a detect control signal generating unit configured to generate a detection sense amplifier control signal for disabling the sense amplifier and a detection precharge control signal for enabling the precharge circuit in response to the detect signal;
• and
• a control signal generating unit configured to generate a precharge control signal for controlling the precharge circuit and a sense amplify control signal for controlling the sense amplifier in response to a read command,
• wherein the control signal generating unit is coupled to the detect control signal generating unit, and
• wherein the detect control signal generating unit comprises:
• a first SR latch configured to receive the precharge control signal on a set input terminal and the detect signal on a reset input terminal to generate the detection precharge control signal;
• and
• a second SR latch configured to receive the sense amplifier control signal on a set input terminal and the detect signal on a reset input terminal to generate the detection sense amplifier control signal.

A memory device comprising:

• a local input/output line pair configured to be coupled to a memory cell and a bit line pair through a first switching circuit;
• a global input/output line pair configured to be coupled to the local input/output line pair through a second switching circuit;
• a precharge circuit configured to precharge the global input/output line pair to a predetermined voltage level;
• a sense amplifier configured to detect and amplify a potential difference between the global input/output line pair;
• a control signal generating unit configured to generate a first switching control signal, a second switching control signal, a precharge circuit control signal and a sense amplifier control signal in response to a read command;
• and
• a detect control signal generating unit coupled to the control signal generating unit, configured to generate a detection precharge control signal for controlling an operation of the precharge circuit and a detection sense amplifier control signal for controlling an operation of the sense amplifier based on the detected potential difference between the global input/output line pair,
• wherein the detect control signal generating unit generates a first detection switching control signal such that the first switching circuit is turned on based on the first switching control signal and such that the first switching circuit is turned off based on the detect signal,
• wherein the detect control signal generating unit generates a second detection switching control signal such that the second switching circuit is turned on based on the second switching control signal and such that the second switching circuit is turned off based on the detect signal, and
• wherein the detect control signal generating unit includes a plurality of SR latches respectively one of which receives a corresponding control signal on a set input terminal and the detect signal on a reset input terminal to generate the detection precharge control signal, the detection sense amplifier control signal and the first and second switching control signals.