Vertical thyristor-based memory with trench isolation and its method of fabrication
AssigneeT-RAM Semiconductor, Inc.
InventorAndrew E. Horch
Life of this patent
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Abstract
A semiconductor device may comprise a plurality of memory cells. A memory cell may comprise a thyristor, at least a portion of which is formed in a pillar of semiconductor material. The pillar may comprise sidewalls defining a cylindrical circumference of a first diameter. In a particular embodiment, the pillars associated with the plurality of memory cells may define rows and columns of an array. In a further embodiment, a pillar may be spaced by a first distance of magnitude up to the first diameter relative to a neighboring pillar within its row. In an additional further embodiment, the pillar may be spaced by a second distance of a magnitude up to twice the first diameter, relative to a neighboring pillar within its column.
Claims13
A semiconductor device, comprising:
- a plurality of thyristor-based memory cells each comprising a thyristor formed in a pillar of semiconductor material that has a cylindrical circumference of a first diameter;
- the pillars associated with the plurality of thyristor-based memory cells defining rows and columns of an array;
- and
- a given pillar of the plurality spaced by a first distance of magnitude up to the first diameter relative to a first pillar of the same row, and
- a second pillar of the plurality spaced from the given pillar by a second distance of magnitude up to twice the first diameter within the same column;
- in which the pillars each further comprise an access device in electrical series relationship and vertically aligned with the associated thyristor.
A semiconductor thyristor-based memory array comprising:
- an array of memory cells comprising a plurality of rows and columns of semiconductor pillars;
- first and second row wordlines comprising respective first and second layers of conductive material;
- the first and the second layers of conductive material vertically offset relative to each other;
- each of the first and the second wordlines for a given row of the semiconductor pillars comprising a plurality of apertures:
- the apertures defined by the first wordline aligned vertically to apertures of the second wordline;
- the pillars of semiconductor material for the given row extending through the aligned apertures;
- and
- dielectric disposed between the pillars and the conductive material of the first and second wordlines;
- in which the semiconductor pillars comprise vertically aligned alternating regions of opposite conductivity type to define at least part of a thyristor in series with an access transistor therein.
A semiconductor thyristor-based memory array comprising:
- an array of memory cells comprising a plurality of rows and columns of semiconductor pillars;
- first and second row wordlines comprising respective first and second layers of conductive material;
- the first and the second layers of conductive material vertically offset relative to each other;
- each of the first and the second wordlines for a given row of the semiconductor pillars comprising a plurality of apertures;
- the apertures defined by the first wordline aligned vertically to apertures of the second wordline;
- the pillars of semiconductor material for the given row extending through the aligned apertures;
- and
- dielectric disposed between the pillars and the conductive material of the first and second wordlines;
- in which;
- the semiconductor pillars comprise vertically aligned alternating regions of opposite conductivity type to define at least part of a thyristor in series with an access transistor therein;
- the conductive material for the first wordline operable collectively as a gate electrode capacitively coupled to a body region of the respective access transistors for the pillars of a given row;
- the layer of conductive material for the second wordline is operable as a capacitor electrode capacitively coupled to a base region of the respective thyristors for the pillars associated with the given row;
- and
- at least one of the first and second wordlines is formed from sleeves of conductive material conformally deposited about the pillars with a radial thickness of magnitude greater than half the distance interspacing the neighboring pillars within the given row.
Dependencies are inferred from the claim text.