Synthesis approach for active leakage power reduction using dynamic supply gating
AssigneePurdue Research Foundation
InventorsSwarup Bhunia, Nilanjan Banerjee, Hamid Mahmoodi, Qikai Chen, Kaushik Roy
Life of this patent
Estimating the term…
Abstract
A logic synthesis method to apply supply gating to idle portions of general logic circuits in their active mode of operation to reduce power requirements and the circuits resulting therefrom. A Shannon expansion is utilized to determine idle portions and active portions of the general logic circuits.
Claims15
A method to control the amount of power used by a combinational logic circuit implementing a logic function, the method comprising the steps of:
- converting the logic function to a sum of at least two sub-functions, to determine an idle portion of the logic circuit and to determine an active portion of the logic circuit according to the Shannon expansion method, wherein one of the at least two sub-functions includes a first control variable and a first cofactor and the other of the at least two sub-functions includes a second control variable and a second cofactor;
- providing a logic circuit including the idle portion and the active portion and a first cofactor circuit based on the first cofactor and a second cofactor circuit based on the second cofactor;
- providing a first control gate coupled to the first cofactor circuit and a second control gate coupled to the second cofactor circuit;
- disconnecting the power from the idle portion of the circuit;
- and
- connecting the power to the active portion of the circuit while the power is disconnected from the idle portion of the circuit.
A method to control the amount of power used by a combinational logic circuit implementing a logic function, the method comprising the steps of:
- converting the logic function to a sum of at least two sub-functions, to determine an idle portion of the logic circuit and to determine an active portion of the logic circuit according to the Shannon expansion method, wherein one of the at least two sub-functions includes a first control variable and a first cofactor and the other of the at least two sub-functions includes a second control variable and a second cofactor;
- identifying one or more minterms not including either of the first cofactor and second cofactor;
- providing a logic circuit including the idle portion and the active portion;
- disconnecting the power from the idle portion of the circuit;
- connecting the power to the active portion of the circuit while the power is disconnected from the idle portion of the circuit;
- and
- further comprising the step of optimizing the logic function prior to the step of converting the logic function to the sum of two sub-functions, to provide a logic function having a minimized number of literals.
A method of providing a combinational logic circuit implementing a logic function, the circuit including a reduced power requirement, the method comprising the steps of:
- optimizing the logic function;
- converting the optimized logic function to a two-level format;
- identifying a control variable, a first cofactor, and a second cofactor from the two level format;
- eliminating a common sub-expression after the identifying step to eliminate a duplicate logic function;
- estimating one or both of an original power and original delay of the optimized logic function
- estimating an estimated power after the eliminating step;
- comparing the original power to the estimated power to determine whether the identified first cofactor and second cofactor have reduced power;
- mapping the first cofactor to provide a first logic circuit including a first output;
- mapping the second cofactor to provide a second logic circuit including a second output;
- and
- coupling the first output and the second output to a selector, to select from one of the first and second outputs.
Dependencies are inferred from the claim text.