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US 7,454,735 B2Granted
ASIC clock floor planning method and structure
AssigneeInternational Business Machines Corporation
InventorsGeetha Arthanari, Keith M. Carrig, Mark R. Lasher, Daniel R. Menard
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Abstract
A method of designing a clock tree in an integrated circuit combines steps of making a list of all clock sinks; positioning a temporary reference insertion point (TIP); grouping the sinks together with structured clock buffers (SCBs) in a set of levels; and moving the SCBs to improve symmetry of the tree. The SCBs may be of several sizes and may be positioned horizontally or vertically and moved within limits to permit the program to calculate a complete tree.
Claims8
A method of designing a clock tree in an integrated circuit, comprising the steps of:
- collecting a set of sink locations in a master list and a set of blocked areas;
- (a) selecting a temporary insertion point (TIP);
- (b) enclosing a sink at a first level farthest from the TIP in a bin that includes a first subset of sinks and remove the first subset of sinks from the master list;
- (c) assigning a first-level structured clock buffer (SCB) to the bin, in which said step (c) of assigning a first-level SCB to the bin comprises the steps of attempting to place a horizontal SCB, then attempting to place a vertical SCB in a central location when a horizontal SCB will not fit in said central location;
- repeating steps (a), (b) and (c) above for the remaining sinks in the first level of buffers and subsequent levels until a root level is reached;
- improving the symmetry of the tree by moving the SCB locations within constraints to concentrate SCBs in rows and columns;
- connecting the root level TIP to lower levels;
- and
- connecting a source (S) of clock signals to the root level TIP.
6 more elements
Dependencies are inferred from the claim text.