Interconnect-aware methodology for integrated circuit design
AssigneeInternational Business Machines Corporation
InventorsAmir Alon, David Goren, Rachel Gordin, Betty Livshitz, Anatoly Sherman, Michael Zelikson
Life of this patent
Estimating the term…
Abstract
An integrated circuit design kit including one or more circuit components topologies, and one or more critical interconnect lines topologies. The interconnect line topologies may be predefined. The kit may further include one or more circuit components models and one or more critical interconnect lines models.
Claims2
A method for modeling a transmission line topology selectable as a design element for a critical interconnect line of an integrated circuit being designed, wherein the integrated circuit is modeled using said critical interconnect lines before the physical layout of the integrated circuit is determined, said critical interconnect line being defined by a set of geometry parameters and capable of carrying analog and mixed signals, wherein said transmission line topology comprises signal return paths therein, the method comprising:
- calculating low frequency RLC values per unit length, wherein the low frequency values are calculated using a model complying with electrostatic and magnetostatic principles for a geometry parameter range;
- calculating high frequency RLC values per unit length, wherein a high frequency limit transverse electromagnetic inductance matrix is calculated from the capacitance using a quasi transverse electromagnetic mode (quasi-TEM) approximation;
- and
- calculating actual RLC values for a reduced RLC network by using the calculated low frequency RLC values and the calculated high frequency RLC values, wherein the reduced RLC network correctly describes the behavior of said transmission line topology across a frequency range of interest;
- and
- constructing an equivalent RLC network for said transmission line topology using the set of geometry parameters and the reduced RLC network, such that the equivalent RLC network is used by a circuit-level simulator to model said critical interconnect lines.
A computer-readable storage device storing a program for causing a computer to execute a method for modeling a transmission line topology selectable as a design element for a circuit interconnect line of an integrated circuit being designed, wherein the integrated circuit is modeled using said critical interconnect lines before the physical layout of the integrated circuit is determined, said critical interconnect line being defined by a set of geometry parameters and capable of carrying analog and mixed signals, wherein said transmission line topology comprises signal return paths therein, said computer program product including:
- computer usable program code for calculating low frequency RLC values per unit length, wherein the low frequency values are calculated using a model complying with electrostatic and magnetostatic principles for a geometry parameter range;
- computer usable program code for calculating high frequency RLC values per unit length, wherein a high frequency limit transverse electromagnetic inductance matrix is calculated from the capacitance using a quasi transverse electromagnetic mode (quasi-TEM) approximation;
- computer usable program code for calculating actual RLC values for a reduced RLC network by using the calculated low frequency RLC values and the calculated high frequency RLC values, wherein the reduced RLC network correctly describes the transmission line topology behavior across a frequency range of interest;
- and
- computer usable program code for constructing an equivalent RLC network for said transmission line topology using the set of geometry parameters and the reduced RLC network, such that the equivalent RLC network is used by a circuit-level simulator to model said critical interconnect lines.
Dependencies are inferred from the claim text.