Methods and apparatuses for designing integrated circuits (ICs) with optimization at register transfer level (RTL) amongst multiple ICs
AssigneeSynopsys, Inc.
InventorsKenneth S. McElvain, Robert Erickson
Life of this patent
Estimating the term…
Abstract
Techniques for designing integrated circuits (ICs) with optimization at register transfer level (RTL) amongst multiple ICs are described herein. According to one embodiment of the invention, a hierarchical resource estimation is performed based on a technology independent register transfer level (RTL) netlist, which is to be partitioned between multiple ICs. Based on the estimation, the RTL netlist is partitioned between the multiple ICs. In response to the partition and the estimation, immediate feedback information is provided to a user.
Claims36
A method of designing a plurality of integrated circuits (ICs), the method comprising:
- dragging and dropping a portion of a technology independent register transfer level (RTL) netlist onto a target IC through a graphical user interface (GUI) on a display device;
- performing a hierarchical resource estimation based on the RTL netlist which is to be partitioned between the plurality of ICs including between the target IC and at least one other IC, wherein the estimation is performed upon receiving the dropping of the portion of the RTL netlist as the target IC;
- partitioning said RTL netlist between said plurality of ICs;
- and
- providing immediate feedback information to a user based on the estimation in response to said partitioning, wherein the feedback information is displayed on the display device.
A machine readable medium (MRM) containing a plurality of executable instructions, which when executed on a digital processing system cause said digital processing system to perform a method of designing a plurality of integrated circuits (ICs), the method comprising:
- dragging and dropping a portion of a technology independent register transfer level (RTL) netlist onto a target IC through a graphical user interface (GUI) on a display device;
- performing a hierarchical resource estimation based on the RTL netlist which is to be partitioned between the plurality of ICs including between the target IC and at least one other IC, wherein the estimation is performed upon receiving the dropping of the portion of the RTL netlist at the target IC;
- partitioning said RTL netlist between said plurality of ICs;
- and
- providing immediate feedback information to a user based on the estimation in response to said partitioning, wherein the feedback information is displayed on the display device.
A system for designing a plurality of integrated circuits (ICs), the system comprising:
- means for dragging and dropping a portion of a technology independent register transfer level (RTL) netlist onto a target IC through a graphical user interface (GUI) on a display device;
- means for performing a hierarchical resource estimation based on the RTL netlist which is to be partitioned between the plurality of ICs including between the target IC and at least one other IC, wherein the estimation is performed upon receiving the dropping of the portion of the RTL netlist at the target IC;
- means for partitioning said RTL netlist between said plurality of ICs;
- and
- means for providing immediate feedback information to a user based on the estimation in response to said partitioning, wherein the feedback information is displayed on the display device.
Dependencies are inferred from the claim text.