Repeater insertion for concurrent setup time and hold time violations
AssigneeSun Microsystems, Inc.
InventorSalim U. Chowdhury
Life of this patent
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Abstract
A method for inserting repeaters into an integrated circuit synthesis is provided. The method initiates with identifying possible repeater insertion locations along a signal routing pathway within an integrated circuit design. The possible repeater insertion locations are organized in a tree enabling bottom-up traversal. A set of solutions for each of the insertion locations is generated while traversing the tree in a first direction and the set of solutions is organized in a first and a second set, the first set ordered by a late mode capacitive load and the second set order by an early mode capacitive load. A computer readable medium including program instructions representing the method operations and a system are also included.
Claims21
A method for inserting repeaters into an integrated circuit synthesis comprising method operations of:
- identifying possible repeater insertion locations along a signal routing pathway within an integrated circuit design;
- organizing the possible repeater insertion locations in a tree enabling bottom-up traversal;
- generating a set of solutions for each of the insertion locations while traversing the tree in a first direction, considering both set up time and hold time concurrently when generating the set of solutions, identifying solutions that are non sub-optimal in a late mode and solution that are non sub-optimal in an early mode, identifying combinations of solutions that are non sub-optimal in the late mode and combinations of solutions that are non sub-optimal in the early mode, identifying combinations common to both combinations of solutions and eliminating the combinations common to both combinations of solutions;
- and
- organizing the set of solutions in a first and a second set, the first set ordered by a late mode capacitive load and the second set order by an early mode capacitive load.
A computer readable medium having program instructions for inserting repeaters into an integrated circuit synthesis comprising:
- program instructions for identifying possible repeater insertion locations along a signal routing pathway within an integrated circuit design;
- program instructions for organizing the possible repeater insertion locations in a tree enabling bottom-up traversal;
- program instructions for generating a set of solutions for each of the insertion locations while traversing the tree in a first direction, considering both set up time and hold time concurrently when generating the set of solutions, identifying solutions that are non sub-optimal in a late mode and solution that are non sub-optimal in an early mode, identifying combinations of solutions that are non sub-optimal in the late mode and combinations of solutions that are non sub-optimal in the early mode, identifying combinations common to both combinations of solutions and eliminating the combinations common to both combinations of solutions;
- and
- program instructions for organizing the set of solutions in a first and a second set, the first set ordered by a late mode capacitive load and the second set order by an early mode capacitive load.
A system for designing an integrated circuit, the system comprising:
- a bus;
- a memory;
- a monitor configured to display a design of the integrated circuit;
- a processor in communication with the memory and the monitor through the bus, the processor operable to receive instructions which, when executed by the processor, cause the processor to perform a method operations comprising:
- identifying possible repeater insertion locations along a signal routing pathway within an integrated circuit design;
- organizing the possible repeater insertion locations in a tree enabling bottom-up traversal;
- generating a set of solutions for each of the insertion locations while traversing the tree in a first direction and both a set up time and a hold time are considered concurrently when generating the set of solutions, identifying solutions that are non sub-optimal in a late mode and solution that are non sub-optimal in an early mode, identifying combinations of solutions that are non sub-optimal in the late mode and combinations of solutions that are non sub-optimal in the early mode, identifying combinations common to both combinations of solutions and eliminating the combinations common to both combinations of solutions;
- and
- organizing the set of solutions in a first and a second set, the first set ordered by a late mode capacitive load and the second set order by an early mode capacitive load.
A method for inserting repeaters into an integrated circuit synthesis comprising method operations of:
- identifying possible repeater insertion locations along a signal routing pathway within an integrated circuit design;
- organizing the possible repeater insertion locations in a tree enabling bottom-up traversal;
- generating a set of solutions for each of the insertion locations while traversing the tree in a bottom-up direction;
- organizing non sub-optimal solutions in multiple sets, the multiple sets being ordered by one of a late mode capacitive load or an early mode capacitive load;
- identifying an intersection of the multiple sets;
- and
- comparing solutions in the intersection with a solution of the generated set of solutions.
Dependencies are inferred from the claim text.