Method and system for validating testbench

A computing system for determining timing violations in a testbench comprising:

• a processor;
• and
• a memory in communication with the processor over a bus, the memory includes program instructions to be executed by the processor, the program instructions causing the processor to perform a method comprising:
• obtaining timing requirements of a design under test from a first file;
• performing place and route operations based on the timing requirements, the place and route operation resulting in a design layout;
• obtaining timing results following the place and route for the design layout;
• automatically extracting timing components from the timing results;
• calculating timing values at an input pin level from the timing components, the calculating including introducing a dummy register into a testbench checker wrapper file, wherein the dummy register is capable of receiving a data signal and a clock signal directly from an input pin and a clock, respectively;
• and
• driving an input for the input pin based on the timing values.

A computer program embodied on a computer readable medium for validating violations in a testbench comprising:

• a code segment for obtaining timing requirements from a first file;
• a code segment for performing place and route operation of circuit elements based on the timing requirements resulting in a design layout;
• a code segment for obtaining timing results of the design layout from an output of a simulation tool;
• a code segment for extracting timing components from the timing results;
• a code segment for deriving timing values from the timing components for an input pin, the code segment for deriving including a code segment for introducing a dummy register into a testbench checker wrapper file, wherein the dummy register is capable of receiving a data signal and a clock signal directly from the input pin and a clock, respectively;
• and
• a code segment for driving the input pin based on the timing value.