Technique for generating input stimulus to cover properties not covered in random simulation
AssigneeSun Microsystems, Inc.
InventorsWilliam K. Lam, Yick Kei Wong, Harihara Ganesan
Life of this patent
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Abstract
A design of an integrated circuit is first verified using directed and/or random test cases. For a cover directive not covered by the directed and/or random test cases, a property is created, where a simulation trace that causes the property to fail covers the cover directive. Thereafter, the property is evaluated, and dependent on the evaluation, the simulation trace is dumped and stored for subsequent exercising of the cover directive.
Claims17
A method of verifying a design of an integrated circuit, comprising:
- at least one of simulating a plurality of random test cases for the design and simulating a plurality of directed test cases for the design;
- identifying a cover directive not covered by the simulating the plurality of random tests and the simulating the plurality of directed test cases;
- creating a property dependent on the identifying, wherein constraints are applied to one or more inputs or internal signals of the design, and a simulation trace that causes the property to fail covers the cover directive;
- evaluating the property;
- and
- storing the simulation trace based on the evaluating;
- wherein the property being defined as a sum of !C, !A1, !A2, and !Ai,
- C comprises a condition being tested, and
- A1,A2, and Airepresent constraints that each evaluate high when passing.
A computer system, comprising:
- a processor;
- a memory operatively connected to the processor;
- and
- instructions residing in the memory and executable by the processor, the instructions comprising instructions to:
- at least one of simulate a plurality of random test cases for a design of an integrated circuit and simulate a plurality of directed test cases for the design,
- identify a cover directive not covered by the simulation of the plurality of random tests and the simulation of the plurality of directed test cases,
- create a property dependent on the identification, wherein constraints are applied to one or more inputs or internal signals of the design, and a simulation trace that causes the property to fail covers the cover directive,
- evaluate the property, and
- store the simulation trace based on the evaluation;
- wherein the property being defined as a sum of !C, !A1, !A2, and !Ai,
- C comprises a condition being tested, and
- A1, A2, Airepresent constraints that each evaluate high when passing.
A computer-readable medium having instruction therein, the instructions for:
- at least one of simulating a plurality of random test cases for a design of an integrated circuit and simulating a plurality of directed test cases for the design;
- identifying a cover directive not covered by the simulating the plurality of random tests and the simulating the plurality of directed test cases;
- creating a property dependent on the identifying, wherein constraints arc applied to one or more inputs or internal signals of the design, and a simulation trace that causes the property to fail covers the cover directive;
- evaluating the property;
- and
- storing the simulation trace based on the evaluating;
- wherein the property being defined as a sum of !C, !A1, !A2, and !Ai,
- C comprises a condition being tested, and
- A1, A2, and Ai, represent constraints that each evaluate high when passing.
Dependencies are inferred from the claim text.